(German Title: Kommunikation im objektorientierten Hardwareentwurf am Beispiel von Objective VHDL)

concept for communication between objects. Unfortunately, exactly the communication concept can be identified often as a critical issue in several existing proposals for objectoriented HDLs. Since the object-oriented Modeling Paradigm and the requirements of the hardware design process have strong influence on the development of appropriate communication concepts, a detailed requirements analysis is indispensable. In the OO-COM project several such requirements have been identified. Based on the requirements analysis a new object- and synthesis-oriented communication model was developed. The application of the communication model is shown for the object-oriented hardware description language Objective VHDL. Objective VHDL was developed in the former EU-Project REQUEST with strong contribution of OFFIS. The integration of the new communication model into Objective VHDL rectifies one of the most important shortcomings which had been identified during the evaluation of the language. It was reported that the mechanisms of Objective VHDL to model communication between object-oriented hardware components are not appropriate for the object-oriented modeling level. A very strong argument for the usage of Objective VHDL for object-oriented hardware design is it’s linkage to hardware synthesis. The proposed communication model preserves this property. Since the intention of this report is to give an overview of the OO-COM project, only the results of the project are described in the report. A deeper and more detailed discussion can be found in the thesis of the author. The Title of this thesis is „Durchgängiges Kommunikationsdesign für den strukturalen, objektorientierten Hardwareentwurf“. The thesis is available in german only. 2