Capabilities of technology utilization and technology integration : Impact of 3D technologies on product development process and performance

Multi-functional technologies widely influence on organization and often require organizational technology integration capabilities to achieve the total effectiveness. Technology integration capability here implies not only utilizing technologies in the present setting of organizational environment but also reforming organizational process and structure towards total optimization. This paper aims to exam technology integration capabilities among Japanese and Chinese firms through questionnaire surveys regarding impact of 3D technologies on product development process and performance. The results indicated that Japanese companies improved their total performance with process reformation leveraged by 3D technologies; however, among Chinese companies, no significant relationships were observed among 3D technology usage, process reformation and the total performance improvement although they improve the partial performance such as manufacturability by utilizing the technologies. Chinese companies, which have a huge growing market and are on the process of rapidly improving their productivities without strong organizational inertia, could have enough advantage by utilizing technologies to improve the partial performance. On the other hand, Japanese companies, which compete in mature market and have already had highly efficient organizational process, could not find the merits of technology usage without technology integration capabilities. This would be regarded as disadvantage of process-advanced company that they cannot have enough incentive to introduce advanced technology and new entries have a chance to leap-frog the advanced companies in usage of technology in general.

Layout regularity metric as a fast indicator of process variations

Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Systematic variations induced by different steps in the lithography process affect both parametric and functional yields of the designs. These variations are known, themselves, to be affected by layout topologies. Design for Manufacturability (DFM) aims at defining techniques that mitigate variations and improve yield. Layout regularity is one of the trending techniques suggested by DFM to mitigate process variations effect. There are several solutions to create regular designs, like restricted design rules and regular fabrics. These regular solutions raised the need for a regularity metric. Metrics in literature are insufficient for different reasons; either because they are qualitative or computationally intensive. Furthermore, there is no study relating either lithography or electrical variations to layout regularity. In this work, layout regularity is studied in details and a new geometrical-based layout regularity metric is derived. This metric is verified against lithographic simulations and shows good correlation. Calculation of the metric takes only few minutes on 1mm x 1mm design, which is considered fast compared to the time taken by simulations. This makes it a good candidate for pre-processing the layout data and selecting certain areas of interest for lithographic simulations for faster throughput. The layout regularity metric is also compared against a model that measures electrical variations due to systematic lithographic variations. The validity of using the regularity metric to flag circuits that have high variability using the developed electrical variations model is shown. The regularity metric results compared to the electrical variability model results show matching percentage that can reach 80%, which means that this metric can be used as a fast indicator of designs more susceptible to lithography and hence electrical variations

Design guidelines towards compact litho-friendly regular cells

Preprin

Modular Product Architecture’s Decisions Support For Remanufacturing-Product Service System Synergy

Remanufacturing is identified as the most viable product end-of-life (EOL) management strategy. However, about 80% of manufactured products currently end up as wastes. Besides other benefits, the product service system (PSS) could curtail the main bottlenecks to remanufacturing namely quantity, quality, recovery time of used product, and negative perception of remanufactured products. Therefore, the integration of PSS and remanufacturing has been increasingly recommended as an enhanced product offering. However, an integration that is informed by mathematical analysis is missing. Meanwhile, the variables that bolster the performance of PSS and remanufacturing are substantially influenced by product development (PD) decisions. Among the PD strategies, modular architecture is a technique that significantly enhances product lifecycle management. Consequently, modular design is a suitable PD approach for an enhanced PSS-remanufacturing enterprise. Furthermore, it is argued that the PSS-remanufacturing initiative is poised to be a sustainable venture due to the sustainability philosophy of PSS. However, the acclaimed sustainability of PSS is flawed if a high environmental impact is associated with the production of the parts that constitute the product which is offered in PSS. Therefore, it is essential to consider the environmental implications of the production of the parts that are contained in the product architecture during PD. This research identifies that cost, core-cleaning, and product serviceability are critical variables for the success of remanufacturing and PSS. The research employs pairwise assessment methodology to evaluate the compatibility of module pairs comprehensively and obtains the modular pair compatibility indices via fuzzy system. Similarly, cost data are obtained. The study develops an optimization model that determines viable modular configuration(s) from among several alternatives in order to realize an enhanced PSS-remanufacturing business. Furthermore, the research performs lifecycle assessment (LCA) of module variants and determine the modular architecture with minimal environmental Impact. Having obtained the optimal architectures with regard to cost, core cleaning, product serviceability and environmental impacts, multi-attribute utility theory (MAUT) is engaged to collectively assess the degree of sustainability of the product architectures. The study offers analytical-based guidance to the original equipment manufacturers (OEMs) in making product architecture decisions in order to realize the sustainable PSS-remanufacturing enterprise

Design for manufactureability with regular fabrics in digital integrated circuits

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 113-115).Integrated circuit design is limited by manufacturability. As devices scale down, sensitivity to process variation increases dramatically, making design for manufacturability a critical concern. Designers must identify the designs that generate the least systematic process variation, e.g., from pattern dependent effects, but must also build circuits that are robust to the remaining process or environmental random variations. This research addresses both ideas, by examining integrated circuit design styles and aspects that can help curb process variation and improve manufacturability and performance in future technology generations. One suggested method to reduce variation sensitivity in system designs has been the concept of design regularity. Long used in FPGAs, and SRAMs, the concept of repeatable blocks is examined in this work as a method of reducing circuit variation. Layout based variation is examined in three designs with different distinctions of regularity: a Via-Patterned Gate Array (VPGA) FPU, a Berkeley BEE-generated decoder, and a low power FPGA. The circuit level impact on variation is also considered, by examining several circuit architectures. This includes analysis of the novel Limited Switch Dynamic Logic (LSDL) style, which reduces design area and encourages regularity through minimum logic sizing.(cont.) Robustness to spatial variation and slanted plane effects is examined with a common-centroid based layout methodology for digital integrated circuits. Finally, a methodology is introduced in the form of the Monte Carlo Variation Analysis Engine whereby distributed process variables are fed into repeated simulation runs, output metrics are recorded, and regressions are measured to expose design sensitivities. The results for different layout and circuit design styles identify improvements that may be made to improve robustness to variation. We show that design regularity is a significant factor in mitigating sensitivity to process variation and is worthy of further examination.by Mehdi Gazor.S.M

DFM Techniques for the Detection and Mitigation of Hotspots in Nanometer Technology

With the continuous scaling down of dimensions in advanced technology nodes, process variations are getting worse for each new node. Process variations have a large influence on the quality and yield of the designed and manufactured circuits. There is a growing need for fast and efficient techniques to characterize and mitigate the effects of different sources of process variations on the design's performance and yield. In this thesis we have studied the various sources of systematic process variations and their effects on the circuit, and the various methodologies to combat systematic process variation in the design space. We developed abstract and accurate process variability models, that would model systematic intra-die variations. The models convert the variation in process into variation in electrical parameters of devices and hence variation in circuit performance (timing and leakage) without the need for circuit simulation. And as the analysis and mitigation techniques are studied in different levels of the design ow, we proposed a flow for combating the systematic process variation in nano-meter CMOS technology. By calculating the effects of variability on the electrical performance of circuits we can gauge the importance of the accurate analysis and model-driven corrections. We presented an automated framework that allows the integration of circuit analysis with process variability modeling to optimize the computer intense process simulation steps and optimize the usage of variation mitigation techniques. And we used the results obtained from using this framework to develop a relation between layout regularity and resilience of the devices to process variation. We used these findings to develop a novel technique for fast detection of critical failures (hotspots) resulting from process variation. We showed that our approach is superior to other published techniques in both accuracy and predictability. Finally, we presented an automated method for fixing the lithography hotspots. Our method showed success rate of 99% in fixing hotspots

EDA Solutions for Double Patterning Lithography

Expanding the optical lithography to 32-nm node and beyond is impossible using existing single exposure systems. As such, double patterning lithography (DPL) is the most promising option to generate the required lithography resolution, where the target layout is printed with two separate imaging processes. Among different DPL techniques litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP) methods are the most popular ones, which apply two complete exposure lithography steps and an exposure lithography followed by a chemical imaging process, respectively. To realize double patterning lithography, patterns located within a sub-resolution distance should be assigned to either of the imaging sub-processes, so-called layout decomposition. To achieve the optimal design yield, layout decomposition problem should be solved with respect to characteristics and limitations of the applied DPL method. For example, although patterns can be split between the two sub-masks in the LELE method to generate conflict free masks, this pattern split is not favorable due to its sensitivity to lithography imperfections such as the overlay error. On the other hand, pattern split is forbidden in SADP method because it results in non-resolvable gap failures in the final image. In addition to the functional yield, layout decomposition affects parametric yield of the designs printed by double patterning. To deal with both functional and parametric challenges of DPL in dense and large layouts, EDA solutions for DPL are addressed in this thesis. To this end, we proposed a statistical method to determine the interconnect width and space for the LELE method under the effect of random overlay error. In addition to yield maximization and achieving near-optimal trade-off between different parametric requirements, the proposed method provides valuable insight about the trend of parametric and functional yields in future technology nodes. Next, we focused on self-aligned double patterning and proposed layout design and decomposition methods to provide SADP-compatible layouts and litho-friendly decomposed layouts. Precisely, a grid-based ILP formulation of SADP decomposition was proposed to avoid decomposition conflicts and improve overall printability of layout patterns. To overcome the limited applicability of this ILP-based method to fully-decomposable layouts, a partitioning-based method is also proposed which is faster than the grid-based ILP decomposition method too. Moreover, an A∗-based SADP-aware detailed routing method was proposed which performs detailed routing and layout decomposition simultaneously to avoid litho-limited layout configurations. The proposed router preserves the uniformity of pattern density between the two sub-masks of the SADP process. We finally extended our decomposition method for double patterning to triple patterning and formulated SATP decomposition by integer linear programming. In addition to conventional minimum width and spacing constraints, the proposed decomposition method minimizes the mandrel-trim co-defined edges and maximizes the layout features printed by structural spacers to achieve the minimum pattern distortion. This thesis is one of the very early researches that investigates the concept of litho-friendliness in SADP-aware layout design and decomposition. Provided by experimental results, the proposed methods advance prior state-of-the-art algorithms in various aspects. Precisely, the suggested SADP decomposition methods improve total length of sensitive trim edges, total EPE and overall printability of attempted designs. Additionally, our SADP-detailed routing method provides SADP-decomposable layouts in which trim patterns are highly robust to lithography imperfections. The experimental results for SATP decomposition show that total length of overlay-sensitive layout patterns, total EPE and overall printability of the attempted designs are also improved considerably by the proposed decomposition method. Additionally, the methods in this PhD thesis reveal several insights for the upcoming technology nodes which can be considered for improving the manufacturability of these nodes

Design of a Protective Device for Head and Neck Injuries in Football

The goal of the MQP was to create a device to prevent concussions in football. Concussive football impacts were recreated with testing equipment including a guided free falling 70lb helmeted head assembly, a 95lb suspended torso, and a recreated Hybrid III neck and head. Data was collected from accelerometers placed in the struck head. A rotational shock absorber was designed to transfer energy from the impacted head to the body of the player in order to reduce head velocities