24,440 research outputs found
A programmable BIST architecture for clusters of Multiple-Port SRAMs
This paper presents a BIST architecture, based on a single microprogrammable BIST processor and a set of memory wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timin
Overview of Swallow --- A Scalable 480-core System for Investigating the Performance and Energy Efficiency of Many-core Applications and Operating Systems
We present Swallow, a scalable many-core architecture, with a current
configuration of 480 x 32-bit processors.
Swallow is an open-source architecture, designed from the ground up to
deliver scalable increases in usable computational power to allow
experimentation with many-core applications and the operating systems that
support them.
Scalability is enabled by the creation of a tile-able system with a
low-latency interconnect, featuring an attractive communication-to-computation
ratio and the use of a distributed memory configuration.
We analyse the energy and computational and communication performances of
Swallow. The system provides 240GIPS with each core consuming 71--193mW,
dependent on workload. Power consumption per instruction is lower than almost
all systems of comparable scale.
We also show how the use of a distributed operating system (nOS) allows the
easy creation of scalable software to exploit Swallow's potential. Finally, we
show two use case studies: modelling neurons and the overlay of shared memory
on a distributed memory system.Comment: An open source release of the Swallow system design and code will
follow and references to these will be added at a later dat
A First Practical Fully Homomorphic Crypto-Processor Design: The Secret Computer is Nearly Here
Following a sequence of hardware designs for a fully homomorphic
crypto-processor - a general purpose processor that natively runs encrypted
machine code on encrypted data in registers and memory, resulting in encrypted
machine states - proposed by the authors in 2014, we discuss a working
prototype of the first of those, a so-called `pseudo-homomorphic' design. This
processor is in principle safe against physical or software-based attacks by
the owner/operator of the processor on user processes running in it. The
processor is intended as a more secure option for those emerging computing
paradigms that require trust to be placed in computations carried out in remote
locations or overseen by untrusted operators.
The prototype has a single-pipeline superscalar architecture that runs
OpenRISC standard machine code in two distinct modes. The processor runs in the
encrypted mode (the unprivileged, `user' mode, with a long pipeline) at 60-70%
of the speed in the unencrypted mode (the privileged, `supervisor' mode, with a
short pipeline), emitting a completed encrypted instruction every 1.67-1.8
cycles on average in real trials.Comment: 6 pages, draf
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