A Charge-Recycling Scheme and Ultra Low Voltage Self-Startup Charge Pump for Highly Energy Efficient Mixed Signal Systems-On-A-Chip

The advent of battery operated sensor-based electronic systems has provided a pressing need to design energy-efficient, ultra-low power integrated circuits as a means to improve the battery lifetime. This dissertation describes a scheme to lower the power requirement of a digital circuit through the use of charge-recycling and dynamic supply-voltage scaling techniques. The novel charge-recycling scheme proposed in this research demonstrates the feasibility of operating digital circuits using the charge scavenged from the leakage and dynamic load currents inherent to digital design. The proposed scheme efficiently gathers the “ground-bound” charge into storage capacitor banks. This reclaimed charge is then subsequently recycled to power the source digital circuit. The charge-recycling methodology has been implemented on a 12-bit Gray-code counter operating at frequencies of less than 50 MHz. The circuit has been designed in a 90-nm process and measurement results reveal more than 41% reduction in the average energy consumption of the counter. The total energy savings including the power consumed for the generation of control signals aggregates to an average of 23%. The proposed methodology can be applied to an existing digital path without any design change to the circuit but with only small loss to the performance. Potential applications of this scheme are described, specifically in wide-temperature dynamic power reduction and as a source for energy harvesters. The second part of this dissertation deals with the design and development of a self-starting, ultra-low voltage, switched-capacitor (SC) DC-DC converter that is essential to an energy harvesting system. The proposed charge-pump based SC-converter operates from 125-mV input and thus enables battery-less operation in ultra-low voltage energy harvesters. The charge pump does not require any external components or expensive post-fabrication processing to enable low-voltage operation. This design has been implemented in a 130-nm CMOS process. While the proposed charge pump provides significant efficiency enhancement in energy harvesters, it can also be incorporated within charge recycling systems to facilitate adaptable charge-recycling levels. In total, this dissertation provides key components needed for highly energy-efficient mixed signal systems-on-a-chip

Power management systems based on switched-capacitor DC-DC converter for low-power wearable applications

The highly efficient ultra-low-power management unit is essential in powering low-power wearable electronics. Such devices are powered by a single input source, either by a battery or with the help of a renewable energy source. Thus, there is a demand for an energy conversion unit, in this case, a DC-DC converter, which can perform either step-up or step-down conversions to provide the required voltage at the load. Energy scavenging with a boost converter is an intriguing choice since it removes the necessity of bulky batteries and considerably extends the battery life. Wearable devices are typically powered by a monolithic battery. The commonly available battery such as Alkaline or Lithium-ion, degrade over time due to their life spans as it is limited by the number of charge cycles- which depend highly on the environmental and loading condition. Thus, once it reaches the maximum number of life cycles, the battery needs to be replaced. The operation of the wearable devices is limited by usable duration, which depends on the energy density of the battery. Once the stored energy is depleted, the operation of wearable devices is also affected, and hence it needs to be recharged. The energy harvesters- which gather the available energy from the surroundings, however, have no limitation on operating life. The application can become battery-less given that harvestable energy is sufficiently powering the low-power devices. Although the energy harvester may not completely replace the battery source, it ensures the maximum duration of use and assists to become autonomous and self-sustain devices. The photovoltaic (PV) cell is a promising candidate as a hypothetical input supply source among the energy harvesters due to its smaller area and high power density over other harvesters. Solar energy use PV harvester can convert ambient light energy into electrical energy and keep it in the storage device. The harvested output of PV cannot directly connect to wearable loads for two main reasons. Depending on the incoming light, the harvested current result in varying open-circuit voltage. It requires the power management circuit to deal with unregulated input variation. Second, depending on the PV cell's material type and an effective area, the I-V characteristic's performance varies, resulting in a variation of the output power. There are several works of maximum power point tracking (MPPT) methods that allow the solar energy harvester to achieve optimal harvested power. Therefore, the harvested power depends on the size and usually small area cell is sufficient for micro-watt loads low-powered applications. The available harvested voltage, however, is generally very low-voltage range between 0.4-0.6 V. The voltage ratings of electronics in standard wearable applications operate in 1.8-3 V voltages as described in introduction’s application example section. It is higher than the supply source can offer. The overcome the mismatch voltage between source and supply circuit, a DC-DC boost converter is necessary. The switch-mode converters are favoured over the linear converters due to their highly efficient and small area overhead. The inductive converter in the switch-mode converter is common due to its high-efficiency performance. However, the integration of the inductor in the miniaturised integrated on-chip design tends to be bulky. Therefore, the switched-capacitor approach DC-DC converters will be explored in this research. In the switched-capacitor converter universe, there is plenty of work for single-output designs for various topologies. Most converters are reconfigurable to the different DC voltage levels apart from Dickson and cross-coupled charge pump topologies due to their boosting power stage architecture through a number of stages. However, existing multi-output converters are limited to the fixed gain ratio. This work explores the reconfigurable dual-output converter with adjustable gain to compromise the research gap. The thesis's primary focus is to present the inductor-less, switched-capacitor-based DC-DC converter power management system (PMS) supplied by a varying input of PV energy harvester input source. The PMS should deliver highly efficient regulated voltage conversion ratio (VCR) outputs to low-power wearable electronic devices that constitute multi-function building blocks

Power Management Techniques for Supercapacitor Based IoT Applications

University of Minnesota Ph.D. dissertation. January 2018. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); xi, 89 pages.The emerging internet of things (IoT) technology will connect many untethered devices, e.g. sensors, RFIDs and wearable devices, to improve health lifestyle, automotive, smart buildings, etc. This thesis proposes one typical application of IoT: RFID for blood temperature monitoring. Once the blood is donated and sealed in a blood bag, it is required to be stored in a certain temperature range (+2~+6°C for red cell component) before distribution. The proposed RFID tag is intended to be attached to the blood bag and continuously monitor the environmental temperature during transportation and storage. When a reader approaches, the temperature data is read out and the tag is fully recharged wirelessly within 2 minutes. Once the blood is distributed, the tag can be reset and reused again. Such a biomedical application has a strong aversion to toxic chemicals, so a batteryless design is required for the RFID tag. A passive RFID tag, however, cannot meet the longevity requirement for the monitoring system (at least 1 week). The solution of this thesis is using a supercapacitor (supercap) instead of a battery as the power supply, which not only lacks toxic heavy metals, but also has quicker charge time (~1000x over batteries), larger operating temperature range (-40~+65°C), and nearly infinite shelf life. Although nearly perfect for this RFID application, a supercap has its own disadvantages: lower energy density (~30x smaller than batteries) and unstable output voltage. To solve the quick charging and long lasting requirements of the RFID system, and to overcome the intrinsic disadvantages of supercaps, an overall power management solution is proposed in this thesis. A reconfigurable switched-capacitor DC-DC converter is proposed to convert the unstable supercap's voltage (3.5V~0.5V) to a stable 1V output voltage efficiently to power the subsequent circuits. With the help of the 6 conversion ratios (3 step-ups, 3 step-downs), voltage protection techniques, and low power designs, the converter can extract 98% of the stored energy from the supercap, and increase initial energy by 96%. Another switched-inductor buck-boost converter is designed to harvest the ambient RF energy to charge the supercap quickly. Because of the variation of the reader distance and incident wave angle, the input power level also has large fluctuation (5uW~5mW). The harvester handles this large power range by a power estimator enhanced MPPT controller with an adaptive integration capacitor array. Also, the contradiction between low power and high tracking speed is improved by adaptive MPPT frequency

A series-stacked power delivery architecture with isolated converters for energy efficient data centers

While the Internet is spreading far and wide, the data centers located at the heart of maintaining uninterrupted access to this service continue to grow rapidly. The energy efficiency of data centers has become crucial in our energy limited world and therefore both power distribution and conversion methods for future data centers need to be reconsidered. In this thesis, alternative methods to achieve more power efficient DC power distribution and voltage regulation for future data centers are investigated. The conventional way of delivering DC power to a server rack in data centers generally contains a central converter that regulates a DC bus, which is typically at 380V rectified grid voltage. This 380V bus voltage is in turn fed to each server rack and one DC-DC converter per server then converts the DC bus voltage to a lower voltage, which is typically 12V. Since each DC-DC converter has to perform a large voltage step down, relatively high power losses are common. In order to avoid large voltage step down and the corresponding power losses of each server’s DC-DC converter, the concept of electrical series stacking of servers in a rack is proposed in this work. The concept of series stacking and active load balancing using differential power processing (DPP) ensures that only the power difference between servers needs to be processed. Therefore the amount of processed power, as well as the power lost during the conversion, is reduced in comparison to the conventional system, where each server’s DC-DC converter has to process all the power needed by the server. This results in a significant reduction in power conversion losses. The concept of series stacking and active voltage balancing by DPP is experimental validated. A DC power distribution system for a four-server rack is created. A control algorithm is developed for server to virtual bus differential power processing and the proposed solution is also supported with experimental results. This thesis presents an experimental demonstration of a series stacked server power delivery architecture with active voltage balancing for future data centers

Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes

Bidirectional neural interfaces are tools designed to “communicate” with the brain via recording and modulation of neuronal activity. The bidirectional interface systems have been adopted for many applications. Neuroscientists employ them to map neuronal circuits through precise stimulation and recording. Medical doctors deploy them as adaptable medical devices which control therapeutic stimulation parameters based on monitoring real-time neural activity. Brain-machine-interface (BMI) researchers use neural interfaces to bypass the nervous system and directly control neuroprosthetics or brain-computer-interface (BCI) spellers. In bidirectional interfaces, the implantable transducers as well as the corresponding electronic circuits and systems face several challenges. A high channel count, low power consumption, and reduced system size are desirable for potential chronic deployment and wider applicability. Moreover, a neural interface designed for robust closed-loop operation requires the mitigation of stimulation artifacts which corrupt the recorded signals. This dissertation introduces several techniques targeting low power consumption, small size, and reduction of stimulation artifacts. These techniques are implemented for extracellular electrophysiological recording and two stimulation modalities: direct current stimulation for closed-loop control of seizure detection/quench and optical stimulation for optogenetic studies. While the two modalities differ in their mechanisms, hardware implementation, and applications, they share many crucial system-level challenges. The first method aims at solving the critical issue of stimulation artifacts saturating the preamplifier in the recording front-end. To prevent saturation, a novel mixed-signal stimulation artifact cancellation circuit is devised to subtract the artifact before amplification and maintain the standard input range of a power-hungry preamplifier. Additional novel techniques have been also implemented to lower the noise and power consumption. A common average referencing (CAR) front-end circuit eliminates the cross-channel common mode noise by averaging and subtracting it in analog domain. A range-adapting SAR ADC saves additional power by eliminating unnecessary conversion cycles when the input signal is small. Measurements of an integrated circuit (IC) prototype demonstrate the attenuation of stimulation artifacts by up to 42 dB and cross-channel noise suppression by up to 39.8 dB. The power consumption per channel is maintained at 330 nW, while the area per channel is only 0.17 mm2. The second system implements a compact headstage for closed-loop optogenetic stimulation and electrophysiological recording. This design targets a miniaturized form factor, high channel count, and high-precision stimulation control suitable for rodent in-vivo optogenetic studies. Monolithically integrated optoelectrodes (which include 12 µLEDs for optical stimulation and 12 electrical recording sites) are combined with an off-the-shelf recording IC and a custom-designed high-precision LED driver. 32 recording and 12 stimulation channels can be individually accessed and controlled on a small headstage with dimensions of 2.16 x 2.38 x 0.35 cm and mass of 1.9 g. A third system prototype improves the optogenetic headstage prototype by furthering system integration and improving power efficiency facilitating wireless operation. The custom application-specific integrated circuit (ASIC) combines recording and stimulation channels with a power management unit, allowing the system to be powered by an ultra-light Li-ion battery. Additionally, the µLED drivers include a high-resolution arbitrary waveform generation mode for shaping of µLED current pulses to preemptively reduce artifacts. A prototype IC occupies 7.66 mm2, consumes 3.04 mW under typical operating conditions, and the optical pulse shaping scheme can attenuate stimulation artifacts by up to 3x with a Gaussian-rise pulse rise time under 1 ms.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147674/1/mendrela_1.pd

Proceedings of the Scientific-Practical Conference "Research and Development - 2016"

talent management; sensor arrays; automatic speech recognition; dry separation technology; oil production; oil waste; laser technolog

Chapter 34 - Biocompatibility of nanocellulose: Emerging biomedical applications

Nanocellulose already proved to be a highly relevant material for biomedical applications, ensued by its outstanding mechanical properties and, more importantly, its biocompatibility. Nevertheless, despite their previous intensive research, a notable number of emerging applications are still being developed. Interestingly, this drive is not solely based on the nanocellulose features, but also heavily dependent on sustainability. The three core nanocelluloses encompass cellulose nanocrystals (CNCs), cellulose nanofibrils (CNFs), and bacterial nanocellulose (BNC). All these different types of nanocellulose display highly interesting biomedical properties per se, after modification and when used in composite formulations. Novel applications that use nanocellulose includewell-known areas, namely, wound dressings, implants, indwelling medical devices, scaffolds, and novel printed scaffolds. Their cytotoxicity and biocompatibility using recent methodologies are thoroughly analyzed to reinforce their near future applicability. By analyzing the pristine core nanocellulose, none display cytotoxicity. However, CNF has the highest potential to fail long-term biocompatibility since it tends to trigger inflammation. On the other hand, neverdried BNC displays a remarkable biocompatibility. Despite this, all nanocelluloses clearly represent a flag bearer of future superior biomaterials, being elite materials in the urgent replacement of our petrochemical dependence

Improving data center power delivery efficiency and power density with differential power processing and multilevel power converters

Existing data center power delivery architectures consist of many cascaded power conversion stages. The system-level power delivery efficiency decreases each time the requisite power is processed through the individual stages, and the total power converter footprint increases by each cascaded conversion stage. Innovative approaches are investigated in this dissertation for dc-dc step-down conversion and single-phase ac-dc conversion to improve power delivery efficiency and power density in data centers. This dissertation proposes a series-stacked architecture that provides inherently higher efficiency between a dc bus and dc loads through architectural changes, reporting above 99% power delivery efficiencies. The proposed series-stacked architecture increases power delivery efficiency by connecting the dc loads in series to allow the bulk of the requisite power to be delivered without being processed and by reducing overall power conversion using differential power processing. The series-stacked architecture exhibits voltage regulation and hot-swapping while delivering power to rapidly changing computational loads. This dissertation experimentally demonstrates series-stacked power delivery using real-life computational loads in a custom designed four-server rack. In order to provide a complete grid-to-12 V power delivery for data center applications, this dissertation also proposes a buck-type power factor correction converter that yields high power density between a single-phase grid and the dc bus, achieving 79 W/in3 power density. The proposed buck-type power factor correction converter improves power density by eliminating the high-voltage step-down dc-dc conversion stage, which is typically cascaded to boost-type power factor correction converters in conventional data center power delivery architectures, and by leveraging recent developments in flying capacitor multilevel converters using wide-bandgap transistors. The buck-type flying capacitor multilevel power factor correction converter presents a unique operation condition where the flying capacitor voltages are required to follow the input voltage at 50/60 Hz. This dissertation experimentally explores the applicability of such an operation by using a digitally controlled six-level flying capacitor multilevel converter prototype

Integrated Circuit Design for Miniaturized, Trackable, Ultrasound Based Biomedical Implants

This thesis focuses on the design of an ultrasonography compatible implantable sensor platform, as a novel approach that implements a miniaturized, battery-less, real-time trackable parallel biosensing system. In addition to the frontend circuit, a sub-nW fully integrated pH sensor is designed in a way that can be easily integrated with the proposed sonography-compatible sensor platform. Combining the two integrated circuits together, the whole system will be able to map in vivo physiological information acquired from a distributed set of sensors on top of the ultrasound movie, leading to the idea envisioned as “augmented ultrasonography”. Implemented in a 0.18 μm technology, an ultrasound power and data frontend circuit is designed to enable medical sensing implants to operate in an ultrasonography compatible way. When placed within the field of view of an imaging transducer, the frontend circuit harvests the power through a piece of piezo crystal from a minimally modified brightness-mode (B-mode) ultrasound imaging process that is commonly adopted in modern medical practices. The implant can also establish bi-directional data communication channels with the imaging transducer, allowing data to be transmitted in a way synchronized to the frame rate of the B-mode film. The design of the circuit is made possible by a combination of ultra-low-power circuit techniques and novel frontend circuit topologies, as imaging ultrasound waves in the form of short pulses with extremely low duty cycle poses challenges that has not previously seen in other implantable sensor systems. The proposed prototype achieves a total area of 0.6mm² for the integrated circuit (IC), as well as 71mm theoretical maximum implantable depth (up to 40 mm is verified experimentally). These two together give opportunities for this design to become the next generation solution for deep-tissue bio-sensing implants. Realized using the same 0.18 μm technology, the fully integrated pH sensor is designed to deliver accurate pH readouts, at a reasonable speed of 1 sample per second, while consuming only 0.72 nW of power. Using an ion-sensitive field effect transistor (ISFET) and reference field effect transistor pair (REFET), the IC requires minimum additional post fabrication to deliver 10-bit resolution pH readouts at an end-to-end sensitivity of 65.8 LSB/pH. When working as a standalone device, this work advances the state-of-the-art of ISFET based pH sensor design. With an addition of 0.46 mm² of area, it is possible to integrate it with the ultrasound sonography compatible implant platform. This potential integration will further advance the vision of the augmented ultrasonography: real-time display of physiological information in a B-mode film, with the help from a distributed bio-sensor system for deep-tissue physiology monitoring