Fast high--voltage amplifiers for driving electro-optic modulators

We describe five high-voltage (60 to 550V peak to peak), high-speed (1-300ns rise time; 1.3-300MHz bandwidth) linear amplifiers for driving capacitive or resistive loads such as electro-optic modulators. The amplifiers use bipolar transistors in various topologies. Two use electron tubes to overcome the speed limitations of high-voltage semiconductors. All amplifiers have been built. Measured performance data is given for each.Comment: 9pages, 6figures, 6tables, to appear in Review of Scientific Instrument

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

Design and implementation of low power multistage amplifiers and high frequency distributed amplifiers

The advancement in integrated circuit (IC) technology has resulted in scaling down of device sizes and supply voltages without proportionally scaling down the threshold voltage of the MOS transistor. This, coupled with the increasing demand for low power, portable, battery-operated electronic devices, like mobile phones, and laptops provides the impetus for further research towards achieving higher integration on chip and low power consumption. High gain, wide bandwidth amplifiers driving large capacitive loads serve as error amplifiers in low-voltage low drop out regulators in portable devices. This demands low power, low area, and frequency-compensated multistage amplifiers capable of driving large capacitive loads. The first part of the research proposes two power and area efficient frequency compensation schemes: Single Miller Capacitor Compensation (SMC) and Single Miller Capacitor Feedforward Compensation (SMFFC), for multistage amplifiers driving large capacitive loads. The designs have been implemented in a 0.5??m CMOS process. Experimental results show that the SMC and SMFFC amplifiers achieve gain-bandwidth products of 4.6MHz and 9MHz, respectively, when driving a load of 25Kδ/120pF. Each amplifier operates from a ??1V supply, dissipates less than 0.42mW of power and occupies less than 0.02mm2 of silicon area. The inception of the latest IEEE standard like IEEE 802.16 wireless metropolitan area network (WMAN) for 10 -66 GHz range demands wide band amplifiers operating at high frequencies to serve as front-end circuits (e.g. low noise amplifier) in such receiver architectures. Devices used in cascade (multistage amplifiers) can be used to increase the gain but it is achieved at an expense of bandwidth. Distributing the capacitance associated with the input and the output of the device over a ladder structure (which is periodic), rather than considering it to be lumped can achieve an extension of bandwidth without sacrificing gain. This concept which is also known as distributed amplification has been explored in the second part of the research. This work proposes certain guidelines for the design of distributed low noise amplifiers operating at very high frequencies. Noise analysis of the distributed amplifier with real transmission lines is introduced. The analysis for gain and noise figure is verified with simulation results from a 5-stage distributed amplifier implemented in a 0.18??m CMOS process

A Four-stage Power and Area Efficient OTA with 30 × (400pf – 12nf) Capacitive Load Drive Range

Multistage operational transconductance amplifier (OTA) has been a major research focus as a solution to high DC Gain high Gain Bandwidth and wide voltage swing requirement on sub-micron devices. These system requirements, in addition to ultra-large capacitive load drivability (nF-range load capacitor), are useful in applications including LCD drivers, low dropout (LDO) linear regulators, headphone drivers, etc. The major drawback of multistage OTAs is the stability concerns since each added stage introduces low frequency poles. Numerous compensation schemes for three stage OTAs have been proposed in the past decade with only a few four stage OTA in literature. The proposed design is a four stage OTA which uses an active zero block (AZB) to provide left half plane (LHP) zero to help with phase degradation. AZB is embedded in the second stage ensuring reuse of existing block hence providing area and power savings. This design also uses single miller capacitor in the outer loop which ensures improved speed performance with minimal area overhead. A very reliable slew helper is implemented in this design to help with the large signal performance. The slew helper is only operational in the events slewing and does not affect the small signal performance. The proposed design achieves a DC gain of 114 dB, GBW > 1.77MHz and PM > 46.9⁰ for capacitive load ranging from 400pF–12nF (30x) which is the highest recorded range in literature for these type of compensation. It does this by consuming a total power of 143.5µW and an area of 0.007mm^2

High performance building blocks for wireless receiver: multi-stage amplifiers and low noise amplifiers

Different wireless communication systems utilizing different standards and for multiple applications have penetrated the normal people's life, such as Cell phone, Wireless LAN, Bluetooth, Ultra wideband (UWB) and WiMAX systems. The wireless receiver normally serves as the primary part of the system, which heavily influences the system performance. This research concentrates on the designs of several important blocks of the receiver; multi-stage amplifier and low noise amplifier. Two novel multi-stage amplifier typologies are proposed to improve the bandwidth and reduce the silicon area for the application where a large capacitive load exists. They were designed using AMI 0.5 m µ CMOS technology. The simulation and measurement results show they have the best Figure-of-Merits (FOMs) in terms of small signal and large signal performances, with 4.6MHz and 9MHz bandwidth while consuming 0.38mW and 0.4mW power from a 2V power supply. Two Low Noise Amplifiers (LNAs) are proposed, with one designed for narrowband application and the other for UWB application. A noise reduction technique is proposed for the differential cascode Common Source LNA (CS-LNA), which reduces the LNA Noise Figure (NF), increases the LNA gain, and improves the LNA linearity. At the same time, a novel Common Gate LNA (CG-LNA) is proposed for UWB application, which has better linearity, lower power consumption, and reasonable noise performance. Finally a novel practical current injection built-in-test (BIT) technique is proposed for the RF Front-end circuits. If the off-chip component Lg and Rs values are well controlled, the proposed technique can estimate the voltage gain of the LNA with less than 1dB (8%) error

A 5-Gb/s 66 dB CMOS variable-gain amplifier with reconfigurable DC-offset cancellation for multi-standard applications

This paper proposes a variable gain amplifier (VGA) with reconfigurable DC-offset cancellation (DCOC) for multi-standard applications. In this design, a cell-based design method and some bandwidth extension technologies are adopted to achieve a high data rate and a wide gain control range simultaneously. In addition, the DCOC having a tunable lower-cutoff frequency can make an optimum compromise between BER and SNR according to the specified baseband standard. The measurements show that the VGA achieves a gain control range from −6 dB to 60 dB, a bandwidth beyond 3 GHz, and a tunable lower-cutoff frequency from 0 to 300 kHz. When entering a 2 23 −1 pseudo-random bit sequence signal at 5 Gb/s, the VGA consumes 17 mW from a 1.2-V supply and the output data peak-to-peak jitter is less than 40 ps. The VGA is fabricated in a 90-nm CMOS process with a chip size (including all pads) of 0.52×0.5 mm 2

Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage, energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example, including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage, ultra-low-power amplifiers can be designed, preserving, at the same time, excellent small-signal and large-signal performance.Agencia Estatal de Investigación PID2019-107258RB-C32Unión Europea PID2019-107258RB-C3

Energy-efficient amplifiers based on quasi-floating gate techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage ultra low power amplifiers can be designed preserving at the same time excellent small-signal and large-signal performance.This research was funded by AEI/FEDER, grant number PID2019-107258RB-C32

Advanced High Efficiency Architectures for Next Generation Wireless Communications

L'abstract è presente nell'allegato / the abstract is in the attachmen

High-speed Time-interleaved Digital-to-Analog Converter (TI-DAC) for Self-Interference Cancellation Applications

Nowadays, the need for higher data-rate is constantly growing to enhance the quality of the daily communication services. The full-duplex (FD) communication is exemplary method doubling the data-rate compared to half-duplex one. However, part of the strong output signal of the transmitter interferes to the receiver-side because they share the same antenna with limited attenuation and, as a result, the receiver’s performance is corrupted. Hence, it is critical to remove the leakage signal from the receiver’s path by designing another block called self-interference cancellation (SIC). The main goal of this dissertation is to develop the SIC block embedded in the current-mode FD receivers. To this end, the regenerated cancellation current signal is fed to the inputs of the base-band filter and after the mixer of a (direct-conversion) current-mode FD receiver. Since the pattern of the transmitter (the digital signal generated by DSP) is known, a high-speed digital-to-Analog converter (DAC) with medium-resolution can perfectly suppress main part of the leakage on the receiver path. A capacitive DAC (CDAC) is chosen among the available solutions because it is compatible with advanced CMOS technology for high-speed application and the medium-resolution designs. Although the main application of the design is to perform the cancellation, it can also be employed as a stand-alone DAC in the Analog (I/Q) transmitter. The SIC circuitry includes a trans-impedance amplifier (TIA), two DACs, high-speed digital circuits, and built-in-self-test section (BIST). According to the available specification for full-duplex communication system, the resolution and working frequency of the CDAC are calculated (designed) equal to 10-bit (3 binary+ 2 binary + 5 thermometric) and 1GHz, respectively. In order to relax the design of the TIA (settling time of the DAC), the CDAC implements using 2-way time-interleaved (TI) manner (the effective SIC frequency equals 2GHz) without using any calibration technique. The CDAC is also developed with the split-capacitor technique to lower the negative effects of the conventional binary-weighted DAC. By adding one extra capacitor on the left-side of the split-capacitor, LSB-side, the value of the split-capacitor can be chosen as an integer value of the unit capacitor. As a result, it largely enhances the linearity of the CADC and cancellation performance. If the block works as a stand-alone DAC with non-TI mode, the digital input code representing a Sinus waveform with an amplitude 1dB less than full-scale and output frequency around 10.74MHz, chosen by coherent sampling rule, then the ENOB, SINAD, SFDR, and output signal are 9.4-bit, 58.2 dB, 68.4dBc, and -9dBV. The simulated value of the |DNL| (static linearity) is also less than 0.7. The similar simulation was done in the SIC mode while the capacitive-array woks in the TI mode and cancellation current is set to the full-scale. Hence, the amount of cancelling the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. equals 51.3dB, 15.1 dB, 24dBc, 66.4 dB. The designed SIC cannot work as a closed-loop design. The layout was optimally drawn in order to minimize non-linearity, the power-consumption of the decoders, and reduce the complexity of the DAC. By distributing the thermometric cells across the array and using symmetrical switching scheme, the DAC is less subjected to the linear and gradient effect of the oxide. Based on the post-layout simulation results, the deviation of the design after drawing the layout is studied. To compare the results of the schematic and post-layout designs, the exact conditions of simulation above (schematic simulations) are used. When the block works as a stand-alone CDAC, the ENOB, SINAD, SFDR are 8.5-bit, 52.6 dB, 61.3 dBc. The simulated value of the |DNL| (static linearity) is also limited to 1.3. Likewise, the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. are equal to 44dB, 11.7 dB, 19 dBc, 55.7 dB