Bifurcation and chaos in spin-valve pillars in a periodic applied magnetic field

We study the bifurcation and chaos scenario of the macro-magnetization vector in a homogeneous nanoscale-ferromagnetic thin film of the type used in spin-valve pillars. The underlying dynamics is described by a generalized Landau-Lifshitz-Gilbert (LLG) equation. The LLG equation has an especially appealing form under a complex stereographic projection, wherein the qualitative equivalence of an applied field and a spin-current induced torque is transparent. Recently chaotic behavior of such a spin vector has been identified by Zhang and Li using a spin polarized current passing through the pillar of constant polarization direction and periodically varying magnitude, owing to the spin-transfer torque effect. In this paper we show that the same dynamical behavior can be achieved using a periodically varying applied magnetic field, in the presence of a constant DC magnetic field and constant spin current, which is technically much more feasible, and demonstrate numerically the chaotic dynamics in the system for an infinitely thin film. Further, it is noted that in the presence of a nonzero crystal anisotropy field chaotic dynamics occurs at much lower magnitudes of the spin-current and DC applied field.Comment: 8 pages, 7 figures. To appear in Chao

Design of robust spin-transfer torque magnetic random access memories for ultralow power high performance on-chip cache applications

Spin-transfer torque magnetic random access memories (STT-MRAMs) based on magnetic tunnel junction (MTJ) has become the leading candidate for future universal memory technology due to its potential for low power, non-volatile, high speed and extremely good endurance. However, conflicting read and write requirements exist in STT-MRAM technology because the current path during read and write operations are the same. Read and write failures of STT-MRAMs are degraded further under process variations. The focus of this dissertation is to optimize the yield of STT- MRAMs under process variations by employing device-circuit-architecture co-design techniques. A devices-to-systems simulation framework was developed to evaluate the effectiveness of the techniques proposed in this dissertation. An optimization methodology for minimizing the failure probability of 1T-1MTJ STT-MRAM bit-cell by proper selection of bit-cell configuration and access transistor sizing is also proposed. A failure mitigation technique using assistsin 1T-1MTJ STT-MRAM bit-cells is also proposed and discussed. Assist techniques proposed in this dissertation to mitigate write failures either increase the amount of current available to switch the MTJ during write or decrease the required current to switch the MTJ. These techniques achieve significant reduction in bit-cell area and write power with minimal impact on bit-cell failure probability and read power. However, the proposed write assist techniques may be less effective in scaled STT-MRAM bit-cells. Furthermore, read failures need to be overcome and hence, read assist techniques are required. It has been experimentally demonstrated that a class of materials called multiferroics can enable manipulation of magnetization using electric fields via magnetoelectric effects. A read assist technique using an MTJ structure incorporating multiferroic materials is proposed and analyzed. It was found that it is very difficult to overcome the fundamental design issues with 1T-1MTJ STT-MRAM due to the two-terminal nature of the MTJ. Hence, multi-terminal MTJ structures consisting of complementary polarized pinned layers are proposed. Analysis of the proposed MTJ structures shows significant improvement in bit-cell failures. Finally, this dissertation explores two system-level applications enabled by STT-MRAMs, and shows that device-circuit-architecture co-design of STT-MRAMs is required to fully exploit its benefits

Spin-Transfer-Torque (STT) Devices for On-chip Memory and Their Applications to Low-standby Power Systems

With the scaling of CMOS technology, the proportion of the leakage power to total power consumption increases. Leakage may account for almost half of total power consumption in high performance processors. In order to reduce the leakage power, there is an increasing interest in using nonvolatile storage devices for memory applications. Among various promising nonvolatile memory elements, spin-transfer torque magnetic RAM (STT-MRAM) is identified as one of the most attractive alternatives to conventional SRAM. However, several design challenges of STT-MRAM such as shared read and write current paths, single-ended sensing, and high dynamic power are major challenges to be overcome to make it suitable for on-chip memories. To mitigate such problems, we propose a domain wall coupling based spin-transfer torque (DWCSTT) device for on-chip caches. Our proposed DWCSTT bit-cell decouples the read and the write current paths by the electrically-insulating magnetic coupling layer so that we can separately optimize read operation without having an impact on write-ability. In addition, the complementary polarizer structure in the read path of the DWCSTT device allows DWCSTT to enable self-referenced differential sensing. DWCSTT bit-cells improve the write power consumption due to the low electrical resistance of the write current path. Furthermore, we also present three different bit-cell level design techniques of Spin-Orbit Torque MRAM (SOT-MRAM) for alleviating some of the inefficiencies of conventional magnetic memories while maintaining the advantages of spin-orbit torque (SOT) based novel switching mechanism such as low write current requirement and decoupled read and write current path. Our proposed SOT-MRAM with supporting dual read/write ports (1R/1W) can address the issue of high-write latency of STT-MRAM by simultaneous 1R/1W accesses. Second, we propose a new type of SOT-MRAM which uses only one access transistor along with a Schottky diode in order to mitigate the area-overhead caused by two access transistors in conventional SOT-MRAM. Finally, a new design technique of SOT-MRAM is presented to improve the integration density by utilizing a shared bit-line structure

Magnetic Tunnel Junctions based on spinel ZnxFe3-xO4: Magnetic Tunnel Junctions based onspinel ZnxFe3-xO4

Die vorliegende Arbeit befasst sich mit magnetischen Tunnelkontakten (magnetic tunnel junctions, MTJs) auf Basis des Oxids Zinkferrit (ZnxFe3-xO4). Dabei soll das Potential dieses Materials durch die Demonstration des Tunnelmagnetowiderstandes (tunnel magnetoresistance, TMR) in zinkferritbasierten Tunnelkontakten gezeigt werden. Dazu wurde ein Probendesign für MTJs auf Basis der „pseudo spin valve“-Geometrie entwickelt. Die Basis für dieseStrukturen ist ein Dünnfilmstapel aus MgO (Substrat) / TiN / ZnxFe3-xO4 / MgO / Co. Dieser ist mittels gepulster Laserabscheidung (pulsed laser deposition, PLD) hergestellt. Im Rahmen dieser Arbeit wurden die strukturellen, elektrischen und magnetischen Eigenschaften der Dünnfilme untersucht. Des weiteren wurden die fertig prozessierten MTJ-Bauelemente an einem im Rahmen dieser Arbeit entwickeltem und aufgebautem TMR-Messplatz vermessen. Dabei ist es gelungen einen TMR-Effekt von 0.5% in ZnxFe3-xO4-basierten MTJs nachzuweisen. Das erste Kapitel der Arbeit gibt eine Einführung in die spintronischen Effekte Riesenmagnetowiderstand (giant magnetoresistance, GMR) und Tunnelmagnetowiderstand (TMR). Deren technologische Anwendungen sowie die grundlegenden physikalischen Effekte und Modelle werden diskutiert. Das zweite Kapitel gibt eine Übersicht über die Materialklasse der spinellartigen Ferrite. Der Fokus liegt auf den Materialien Magnetit (Fe3O4) sowie Zinkferrit (ZnxFe3-xO4). Die physikalischen Modelle zur Beschreibung der strukturellen, magnetischen und elektrischen Eigenschaften dieser Materialien werden dargelegt sowie ein Literaturüberblick über experimentelle und theoretische Arbeiten gegeben. Im dritten Kapitel werden die im Rahmen dieser Arbeit verwendeten Probenpräparations- und Charakterisierungsmethoden vorgestellt und technische Details sowie physikalische Grundlagen erläutert. Die Entwicklung eines neuen Probendesigns zum Nachweis des TMR-Effekts in ZnxFe3-xO4-basierten MTJs ist Gegenstand des vierten Kapitels. Die Entwicklung des Probenaufbaus sowie die daraus resultierende Probenprozessierung werden beschrieben. Die beiden letzten Kapitel befassen sich mit der strukturellen, elektrischen und magnetischen Charakterisierung der mittels PLD abgeschiedenen Dünnfilme sowie der Tunnelkontaktstrukturen

Energy efficient hybrid computing systems using spin devices

Emerging spin-devices like magnetic tunnel junctions (MTJ\u27s), spin-valves and domain wall magnets (DWM) have opened new avenues for spin-based logic design. This work explored potential computing applications which can exploit such devices for higher energy-efficiency and performance. The proposed applications involve hybrid design schemes, where charge-based devices supplement the spin-devices, to gain large benefits at the system level. As an example, lateral spin valves (LSV) involve switching of nanomagnets using spin-polarized current injection through a metallic channel such as Cu. Such spin-torque based devices possess several interesting properties that can be exploited for ultra-low power computation. Analog characteristic of spin current facilitate non-Boolean computation like majority evaluation that can be used to model a neuron. The magneto-metallic neurons can operate at ultra-low terminal voltage of ∼20mV, thereby resulting in small computation power. Moreover, since nano-magnets inherently act as memory elements, these devices can facilitate integration of logic and memory in interesting ways. The spin based neurons can be integrated with CMOS and other emerging devices leading to different classes of neuromorphic/non-Von-Neumann architectures. The spin-based designs involve `mixed-mode\u27 processing and hence can provide very compact and ultra-low energy solutions for complex computation blocks, both digital as well as analog. Such low-power, hybrid designs can be suitable for various data processing applications like cognitive computing, associative memory, and currentmode on-chip global interconnects. Simulation results for these applications based on device-circuit co-simulation framework predict more than ∼100x improvement in computation energy as compared to state of the art CMOS design, for optimal spin-device parameters

高密度・高速動作可能なSTT-MRAMへ向けたp-MTJのスイッチング過渡現象とアレイ設計指針に関する研究

Tohoku University遠藤哲郎課

Modeling and design for energy-efficient spintronic logic devices and circuits

The objective of the proposed research is the modeling and the design of energy-efficient and scalable novel spintronic devices. Over the past two decades, spintronic devices have achieved special status due to their advantages in terms of low-voltage operation, smaller footprint area, non-volatile memory, and compatibility with CMOS technology. To design efficient spin-based systems, researchers require the precise modeling of the physics of nanomagnets, piezoelectrics, thermal noise, and metallic nanowires. Using the models developed during the research, spintronic logic devices comprised of hybrid magnetic and piezoelectric structures are proposed. The delay, energy dissipation, and footprint area of the proposed devices are analyzed. Moreover, the proposed devices are used as building blocks to propose spin-based logic gates, pattern and image recognition circuits, long-range interconnects, interface circuits, and coupled-oscillators. The performance of the proposed circuits is benchmarked against CMOS and other spin-based circuits, which shows improved performance, especially in implementing non-Boolean applications and interface circuits.Ph.D