Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

With the omnipresence of embedded processing in all forms of electronics today, there is a strong trend towards wireless, battery-powered, portable embedded systems which have to operate under stringent energy constraints. Consequently, low power consumption and high energy efficiency have emerged as the two key criteria for embedded microprocessor design. In this thesis we present a range of microarchitectural low-power design techniques which enable the increase of performance for embedded microprocessors and/or the reduction of energy consumption, e.g., through voltage scaling. In the context of cryptographic applications, we explore the effectiveness of instruction set extensions (ISEs) for a range of different cryptographic hash functions (SHA-3 candidates) on a 16-bit microcontroller architecture (PIC24). Specifically, we demonstrate the effectiveness of light-weight ISEs based on lookup table integration and microcoded instructions using finite state machines for operand and address generation. On-node processing in autonomous wireless sensor node devices requires deeply embedded cores with extremely low power consumption. To address this need, we present TamaRISC, a custom-designed ISA with a corresponding ultra-low-power microarchitecture implementation. The TamaRISC architecture is employed in conjunction with an ISE and standard cell memories to design a sub-threshold capable processor system targeted at compressed sensing applications. We furthermore employ TamaRISC in a hybrid SIMD/MIMD multi-core architecture targeted at moderate to high processing requirements (> 1 MOPS). A range of different microarchitectural techniques for efficient memory organization are presented. Specifically, we introduce a configurable data memory mapping technique for private and shared access, as well as instruction broadcast together with synchronized code execution based on checkpointing. We then study an inherent suboptimality due to the worst-case design principle in synchronous circuits, and introduce the concept of dynamic timing margins. We show that dynamic timing margins exist in microprocessor circuits, and that these margins are to a large extent state-dependent and that they are correlated to the sequences of instruction types which are executed within the processor pipeline. To perform this analysis we propose a circuit/processor characterization flow and tool called dynamic timing analysis. Moreover, this flow is employed in order to devise a high-level instruction set simulation environment for impact-evaluation of timing errors on application performance. The presented approach improves the state of the art significantly in terms of simulation accuracy through the use of statistical fault injection. The dynamic timing margins in microprocessors are then systematically exploited for throughput improvements or energy reductions via our proposed instruction-based dynamic clock adjustment (DCA) technique. To this end, we introduce a 6-stage 32-bit microprocessor with cycle-by-cycle DCA. Besides a comprehensive design flow and simulation environment for evaluation of the DCA approach, we additionally present a silicon prototype of a DCA-enabled OpenRISC microarchitecture fabricated in 28 nm FD-SOI CMOS. The test chip includes a suitable clock generation unit which allows for cycle-by-cycle DCA over a wide range with fine granularity at frequencies exceeding 1 GHz. Measurement results of speedups and power reductions are provided

Dual-frequency single-inductor multiple-output (DF-SIMO) power converter topology for SoC applications

Modern mixed-signal SoCs integrate a large number of sub-systems in a single nanometer CMOS chip. Each sub-system typically requires its own independent and well-isolated power supply. However, to build these power supplies requires many large off-chip passive components, and thus the bill of material, the package pin count, and the printed circuit board area and complexity increase dramatically, leading to higher overall cost. Conventional (single-frequency) Single-Inductor Multiple-Output (SIMO) power converter topology can be employed to reduce the burden of off-chip inductors while producing a large number of outputs. However, this strategy requires even larger off-chip output capacitors than single-output converters due to time multiplexing between the multiple outputs, and thus many of them suffer from cross coupling issues that limit the isolation between the outputs. In this thesis, a Dual-Frequency SIMO (DF-SIMO) buck converter topology is proposed. Unlike conventional SIMO topologies, the DF-SIMO decouples the rate of power conversion at the input stage from the rate of power distribution at the output stage. Switching the input stage at low frequency (~2 MHz) simplifies its design in nanometer CMOS, especially with input voltages higher than 1.2 V, while switching the output stage at higher frequency enables faster output dynamic response, better cross-regulation, and smaller output capacitors without the efficiency and design complexity penalty of switching both the input and output stages at high frequency. Moreover, for output switching frequency higher than 100 MHz, the output capacitors can be small enough to be integrated on-chip. A 5-output 2-MHz/120-MHz design in 45-nm CMOS with 1.8-V input targeting low-power microcontrollers is presented as an application. The outputs vary from 0.6 to 1.6 V, with 4 outputs providing up to 15 mA and one output providing up to 50 mA. The design uses single 10-uH off-chip inductor, 2-nF on-chip capacitor for each 15-mA output and 4.5-nF for the 50-mA output. The peak efficiency is 73%, Dynamic Voltage Scaling (DVS) is 0.6 V/80 ns, and settling time is 30 ns for half-to-full load steps with no observable overshoot/undershoot or cross-coupling transients. The DF-SIMO topology enables realizing multiple efficient power supplies with faster dynamic response, better cross-regulation, and lower overall cost compared to conventional SIMO topologies

Smart energy management and conversion

This chapter introduced power management circuits and energy storage unit designs for sub‐1 mW low power energy harvesting technologies, including indoor light energy harvesting, thermoelectric energy harvesting and vibration energy harvesting. The solutions address several of the problems associated with energy harvesting, power management and storage issues including low voltage operation, self‐start, efficiency (conversion efficiency as well as impact of power consumption of the power management circuit itself), energy density and leakage current levels. Additionally, efforts to miniaturize and integrate magnetic parts as well as integrate discrete circuits onto silicon are outlined to offer improvements in cost, size and efficiency. Finally initial results from efforts to improve energy density of storage devices using nanomaterials are introduced

Circuits and Systems Advances in Near Threshold Computing

Modern society is witnessing a sea change in ubiquitous computing, in which people have embraced computing systems as an indispensable part of day-to-day existence. Computation, storage, and communication abilities of smartphones, for example, have undergone monumental changes over the past decade. However, global emphasis on creating and sustaining green environments is leading to a rapid and ongoing proliferation of edge computing systems and applications. As a broad spectrum of healthcare, home, and transport applications shift to the edge of the network, near-threshold computing (NTC) is emerging as one of the promising low-power computing platforms. An NTC device sets its supply voltage close to its threshold voltage, dramatically reducing the energy consumption. Despite showing substantial promise in terms of energy efficiency, NTC is yet to see widescale commercial adoption. This is because circuits and systems operating with NTC suffer from several problems, including increased sensitivity to process variation, reliability problems, performance degradation, and security vulnerabilities, to name a few. To realize its potential, we need designs, techniques, and solutions to overcome these challenges associated with NTC circuits and systems. The readers of this book will be able to familiarize themselves with recent advances in electronics systems, focusing on near-threshold computing

Low-Power Reconfigurable Sensing Circuitry for the Internet-of-Things Paradigm

With ubiquitous wireless communication via Wi-Fi and nascent 5th Generation mobile communications, more devices -- both smart and traditionally dumb -- will be interconnected than ever before. This burgeoning trend is referred to as the Internet-of-Things. These new sensing opportunities place a larger burden on the underlying circuitry that must operate on finite battery power and/or within energy-constrained environments. New developments of low-power reconfigurable analog sensing platforms like field-programmable analog arrays (FPAAs) present an attractive sensing solution by processing data in the analog domain while staying flexible in design. This work addresses some of the contemporary challenges of low-power wireless sensing via traditional application-specific sensing and with FPAAs. A large emphasis is placed on furthering the development of FPAAs by making them more accessible to designers without a strong integrated-circuit background -- much like FPGAs have done for digital designers

Design and real-time control of shipboard power system testbed

The objective of this thesis is to design and test a small scale testbed for the all-electric shipboard power distribution system. Shipboard power system is increasingly becoming more reconfigurable, and multi-agent systems are developed to automate routine operation and emergency reconfiguration. Underlying algorithms of these systems have been verified using software simulation tools. However, these simulators run in soft realtime by using simple mathematical models to represent the physical system. These models do not incorporate every aspect of the physical system. A testbed provides a cost effective physical environment to verify these algorithms and control techniques in the real world. This testbed, based on the Navy\u27s notional all electric ship, keeps characteristic features of the Office of Naval Research\u27s Integrated Power System. It provides a platform for testing local and distributed controls. Local embedded controllers on the testbed run in hard real-time, and a CAN bus builds the communication networking among them. Performance of the controllers has been verified successfully, and the platform provides an environment that allows prototyping and testing agent-based higher-level controls and decision making entities

RF Location Tracking: A Modular Antenna System Implementation

From the Amazon Prime Air drone delivery service to the usage of unmanned aerial vehicles (UAV) in military operations, recent years have seen the development of autonomous flight technologies becoming one of the major research topics in the drone industry. Tracking the geographic position of drones is a crucial part of any autonomous flight, but the common methods of drone location tracking either have too large of an error margin or require extensive environmental setup. The aforementioned issues are major roadblocks in the advancement of autonomous flight operations. The proposed solution is a new and improved method to track the location of a drone relative to a single reference point. This method will not require any environmental setup and offers a greater degree of precision than the commonly used Global Positioning System (GPS). The designed proof of concept model, which is a completely modular and self-reliant radio-frequency (RF) based location tracking system, was built to show the viability of this new drone tracking method. The tracking system can determine the relative location of a radio-frequency source with only one receiver module. By requiring only one receiver, this tracking system eliminates the need to set up a triangulation zone. Additionally, optimizing the tracking system to generate a location from the RF telemetry signals needed in user-drone communication, the solution effectively presents an efficient manner to track a drone without the need for additional attachments. The proposed solution introduces a novel method that has the potential to vastly improve autonomous flight development and push it to full realization and fruition

A FEASIBILITY STUDY OF HIGH-VOLTAGE COMPARATORS USING SILICON METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS

The overall trend of transistor scaling has resulted in distinct, application-specific manufacturing processes. Two of these specialized devices scaled complementary metal-oxide-semiconductor field-effect transistors (CMOS) and power transistors, typically have inversely related performance in speed, power handling, and size. This work develops a novel comparator circuit to explore the potential benefits of integrating these two technology schemes to achieve improved power handling capabilities for signal processing and communication systems through the development of a Silicon-based high-voltage comparator. The study produced a final circuit with a flat-band gain of 20dB across the high frequency (HF) range with a projected input voltage tolerance above 10V. The development process indicates that the physical characteristics of the power transistor, a laterally-diffused MOSFET (LDMOS), constrains frequency response and therefore, ultimately, comparator performance. Although the demonstrated device does not achieve the target performance, the investigation suggests that integrating the power transistors at the integrated circuit (IC) level is a promising approach to producing a competitive high-voltage Silicon-based comparator.M.S

Power delivery mechanisms for asynchronous loads in energy harvesting systems

PhD ThesisFor systems depending on methods, a fundamental contradiction in the power delivery chain has existed between conventional to supply it. DC/DC conversion (e.g.) has therefore been an integral part of such systems to resolve this contradiction. be made tolerant to a much wider range of Vdd variance. This may open up opportunities for much more energy efficient methods of power delivery. performance of different power delivery mechanisms driving both asynchronous and synchronous loads directly from a harvester source bypassing bulky energy method, which employs a energy from a EH circuit depending on load and source conditions, is developed. through comprehensive comparative analysis. Based on the novel CBB power delivery method, an asynchronous controller is circuits to work with tasks. The successful asynchronous control design drives a case study that is meant to explore relations between power path and task path. To deal with different tasks with variable harvested power, systems may have a range of operation conditions and thus dynamically call for CBB or SCC type power set of capacitors to form CBB or SCC is implemented with economic system size. This work presents an unconventional way of designing a compact-size, quick- circuit overcome large voltage variation in EH systems and implement smart power management for harsh EH environment. The power delivery mechanisms (SCC, employed to help asynchronous- logic-based chip testing and micro-scale EH system demonstrations