100 research outputs found

    Vertical III-V Nanowire Tunnel Field-Effect Transistor

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    In this thesis fabrication and optimization of vertical III-V Tunneling Field-Effect transistors was explored. Usage of vertical nanowires, allows for combination of materials with large lattice mismatch in the same nanowire structure. TFETs in this thesis were fabricated using vertical InAs/GaSb or InAs/InGaAsSb/GaSb nanowires of high material quality. Usage of these material systems allowed for fabrication of devices with staggered and broken band-gap alignment. To fully harvest the benefits from these structures, the fabrication process was optimized. This was performed by exploring different spacer and gate technologies, required for vertical devices. Furthermore, improvement of electrostatics was achieved by reduction of the channel diameter and high-ฮบ interface. Further improvements of the performance were achieved by scaling of the device dimensions such as nanowire lengths, spacer thickness, and gate-length. Used fabrication techniques allowed us to fabricate devices with a channel diameter of 11 nm. By switching from InAs/GaSb to InAs/InGaAsSb/GaSb allowed for optimization of the heterojunction, which allowed us to fabricate devices with record performance, reaching a minimum subthreshold swing of 48 mV/decade and a record high I60 of 0.31 ฮผA/ฮผm at a drive voltage of 0.3 V. Stability of the process allowed us to demonstrate data from a large number of TFETs with ability to operate below the thermal limit of 60 mV/decade. This allowed us to study correlations between important device parameter such as: I60, on-current, subthreshold swing, and off-current. Using transmission electron microscopy, the heterojunction was characterized. Furthermore, TCAD modeling was performed to understand what limits the performance of these devices. Also, electrical measurement of the random telegraph noise allowed us to understand the impact the oxide defects have on highly scaled devices

    ๋†’์€ ์ „๋ฅ˜ ๊ตฌ๋™๋Šฅ๋ ฅ์„ ๊ฐ€์ง€๋Š” SiGe ๋‚˜๋…ธ์‹œํŠธ ๊ตฌ์กฐ์˜ ํ„ฐ๋„๋ง ์ „๊ณ„ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ

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    ํ•™์œ„๋…ผ๋ฌธ (๋ฐ•์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต ๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ •๋ณด๊ณตํ•™๋ถ€, 2021. 2. ๋ฐ•๋ณ‘๊ตญ.The development of very-large-scale integration (VLSI) technology has continuously demanded smaller devices to achieve high integration density for faster computing speed or higher capacity. However, in the recent complementary-metal-oxide-semiconductor (CMOS) technology, simple downsizing the dimension of metal-oxide-semiconductor field-effect transistor (MOSFET) no longer guarantees the boosting performance of IC chips. In particular, static power consumption is not reduced while device size is decreasing because voltage scaling is slowed down at some point. The increased off-current due to short-channel effect (SCE) of MOSFET is a representative cause of the difficulty in voltage scaling. To overcome these fundamental limits of MOSFET, many researchers have been looking for the next generation of FET device over the last ten years. Tunnel field-effect transistor (TFET) has been intensively studied for its steep switching characteristics. Nevertheless, the poor current drivability of TFET is the most serious obstacle to become competitive device for MOSFET. In this thesis, TFET with high current drivability in which above-mentioned problem is significantly solved is proposed. Vertically-stacked SiGe nanosheet channels are used to boost carrier injection and gate control. The fabrication technique to form highly-condensed SiGe nanosheets is introduced. TFET is fabricated with MOSFET with the same structure in the CMOS-compatible process. Both technology-computer-aided-design (TCAD) simulation and experimental results are utilized to support and examine the advantages of proposed TFET. From the perspective of the single device, the improvement in switching characteristics and current drivability are quantitatively and qualitatively analyzed. In addition, the device performance is compared to the benchmark of previously reported TFET and co-fabricated MOSFET. Through those processes, the feasibility of SiGe nanosheet TFET is verified. It is revealed that the proposed SiGe nanosheet TFET has notable steeper switching and low leakage in the low drive voltage as an alternative to conventional MOSFET.์ดˆ๊ณ ๋ฐ€๋„ ์ง‘์ ํšŒ๋กœ ๊ธฐ์ˆ ์˜ ๋ฐœ์ „์€ ๊ณ ์ง‘์ ๋„ ๋‹ฌ์„ฑ์„ ํ†ตํ•ด ๋‹จ์œ„ ์นฉ์˜ ์—ฐ์‚ฐ ์†๋„ ๋ฐ ์šฉ๋Ÿ‰ ํ–ฅ์ƒ์— ๊ธฐ์—ฌํ•  ์†Œํ˜•์˜ ์†Œ์ž๋ฅผ ๋Š์ž„์—†์ด ์š”๊ตฌํ•˜๊ณ  ์žˆ๋‹ค. ํ•˜์ง€๋งŒ ์ตœ์‹ ์˜ ์ƒ๋ณดํ˜• ๊ธˆ์†-์‚ฐํ™”๋ง‰-๋ฐ˜๋„์ฒด (CMOS) ๊ธฐ์ˆ ์—์„œ ๊ธˆ์†-์‚ฐํ™”๋ง‰-๋ฐ˜๋„์ฒด ์ „๊ณ„ ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ (MOSFET) ์˜ ๋‹จ์ˆœํ•œ ์†Œํ˜•ํ™”๋Š” ๋” ์ด์ƒ ์ง‘์ ํšŒ๋กœ์˜ ์„ฑ๋Šฅ ํ–ฅ์ƒ์„ ๋ณด์žฅํ•ด ์ฃผ์ง€ ๋ชปํ•˜๊ณ  ์žˆ๋‹ค. ํŠนํžˆ ์†Œ์ž์˜ ํฌ๊ธฐ๊ฐ€ ์ค„์–ด๋“œ๋Š” ๋ฐ˜๋ฉด ์ •์  ์ „๋ ฅ ์†Œ๋ชจ๋Ÿ‰์€ ์ „์•• ์Šค์ผ€์ผ๋ง์˜ ๋‘”ํ™”๋กœ ์ธํ•ด ๊ฐ์†Œ๋˜์ง€ ์•Š๊ณ  ์žˆ๋Š” ์ƒํ™ฉ์ด๋‹ค. MOSFET์˜ ์งง์€ ์ฑ„๋„ ํšจ๊ณผ๋กœ ์ธํ•ด ์ฆ๊ฐ€๋œ ๋ˆ„์„ค ์ „๋ฅ˜๊ฐ€ ์ „์•• ์Šค์ผ€์ผ๋ง์˜ ์–ด๋ ค์›€์„ ์ฃผ๋Š” ๋Œ€ํ‘œ์  ์›์ธ์œผ๋กœ ๊ผฝํžŒ๋‹ค. ์ด๋Ÿฌํ•œ ๊ทผ๋ณธ์ ์ธ MOSFET์˜ ํ•œ๊ณ„๋ฅผ ๊ทน๋ณตํ•˜๊ธฐ ์œ„ํ•˜์—ฌ ์ง€๋‚œ 10์—ฌ๋…„๊ฐ„ ์ƒˆ๋กœ์šด ๋‹จ๊ณ„์˜ ์ „๊ณ„ ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ ์†Œ์ž๋“ค์ด ์—ฐ๊ตฌ๋˜๊ณ  ์žˆ๋‹ค. ๊ทธ ์ค‘ ํ„ฐ๋„ ์ „๊ณ„ ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ(TFET)์€ ๊ทธ ํŠน์œ ์˜ ์šฐ์ˆ˜ํ•œ ์ „์› ํŠน์„ฑ์œผ๋กœ ๊ฐ๊ด‘๋ฐ›์•„ ์ง‘์ค‘์ ์œผ๋กœ ์—ฐ๊ตฌ๋˜๊ณ  ์žˆ๋‹ค. ๋งŽ์€ ์—ฐ๊ตฌ์—๋„ ๋ถˆ๊ตฌํ•˜๊ณ , TFET์˜ ๋ถ€์กฑํ•œ ์ „๋ฅ˜ ๊ตฌ๋™ ๋Šฅ๋ ฅ์€ MOSFET์˜ ๋Œ€์ฒด์žฌ๋กœ ์ž๋ฆฌ๋งค๊น€ํ•˜๋Š” ๋ฐ ๊ฐ€์žฅ ํฐ ๋ฌธ์ œ์ ์ด ๋˜๊ณ  ์žˆ๋‹ค. ๋ณธ ํ•™์œ„๋…ผ๋ฌธ์—์„œ๋Š” ์ƒ๊ธฐ๋œ ๋ฌธ์ œ์ ์„ ํ•ด๊ฒฐํ•  ์ˆ˜ ์žˆ๋Š” ์šฐ์ˆ˜ํ•œ ์ „๋ฅ˜ ๊ตฌ๋™ ๋Šฅ๋ ฅ์„ ๊ฐ€์ง„ TFET์ด ์ œ์•ˆ๋˜์—ˆ๋‹ค. ๋ฐ˜์†ก์ž ์œ ์ž…๊ณผ ๊ฒŒ์ดํŠธ ์ปจํŠธ๋กค์„ ํ–ฅ์ƒ์‹œํ‚ฌ ์ˆ˜ ์žˆ๋Š” ์ˆ˜์ง ์ ์ธต๋œ ์‹ค๋ฆฌ์ฝ˜์ €๋งˆ๋Š„(SiGe) ๋‚˜๋…ธ์‹œํŠธ ์ฑ„๋„์ด ์‚ฌ์šฉ๋˜์—ˆ๋‹ค. ๋˜ํ•œ, ์ œ์•ˆ๋œ TFET์€ CMOS ๊ธฐ๋ฐ˜ ๊ณต์ •์„ ํ™œ์šฉํ•˜์—ฌ MOSFET๊ณผ ํ•จ๊ป˜ ์ œ์ž‘๋˜์—ˆ๋‹ค. ํ…Œํฌ๋†€๋กœ์ง€ ์ปดํ“จํ„ฐ ์ง€์› ์„ค๊ณ„(TCAD) ์‹œ๋ฎฌ๋ ˆ์ด์…˜๊ณผ ์‹ค์ œ ์ธก์ • ๊ฒฐ๊ณผ๋ฅผ ํ™œ์šฉํ•˜์—ฌ ์ œ์•ˆ๋œ ์†Œ์ž์˜ ์šฐ์ˆ˜์„ฑ์„ ๊ฒ€์ฆํ•˜์˜€๋‹ค. ๋‹จ์œ„ CMOS ์†Œ์ž์˜ ๊ด€์ ์—์„œ, ์ „์› ํŠน์„ฑ๊ณผ ์ „๋ฅ˜ ๊ตฌ๋™ ๋Šฅ๋ ฅ์˜ ํ–ฅ์ƒ์„ ์ •๋Ÿ‰์ , ์ •์„ฑ์  ๋ฐฉ๋ฒ•์œผ๋กœ ๋ถ„์„ํ•˜์˜€๋‹ค. ๊ทธ๋ฆฌ๊ณ , ์ œ์ž‘๋œ ์†Œ์ž์˜ ์„ฑ๋Šฅ์„ ๊ธฐ์กด ์ œ์ž‘ ๋ฐ ๋ณด๊ณ ๋œ TFET ๋ฐ ํ•จ๊ป˜ ์ œ์ž‘๋œ MOSSFET๊ณผ ๋น„๊ตํ•˜์˜€๋‹ค. ์ด๋Ÿฌํ•œ ๊ณผ์ •์„ ํ†ตํ•ด, ์‹ค๋ฆฌ์ฝ˜์ €๋งˆ๋Š„ ๋‚˜๋…ธ์‹œํŠธ TFET์˜ ํ™œ์šฉ ๊ฐ€๋Šฅ์„ฑ์ด ์ž…์ฆ๋˜์—ˆ๋‹ค. ์ œ์•ˆ๋œ ์‹ค๋ฆฌ์ฝ˜์ €๋งˆ๋Š„ ๋‚˜๋…ธ์‹œํŠธ ์†Œ์ž๋Š” ์ฃผ๋ชฉํ•  ๋งŒํ•œ ์ „์› ํŠน์„ฑ์„ ๊ฐ€์กŒ๊ณ  ์ €์ „์•• ๊ตฌ๋™ ํ™˜๊ฒฝ์—์„œ ํ•œ์ธต ๋” ๋‚ฎ์€ ๋ˆ„์„ค ์ „๋ฅ˜๋ฅผ ๊ฐ€์ง์œผ๋กœ์จ ํ–ฅํ›„ MOSFET์„ ๋Œ€์ฒดํ• ๋งŒํ•œ ์ถฉ๋ถ„ํ•œ ๊ฐ€๋Šฅ์„ฑ์„ ๋ณด์—ฌ์ฃผ์—ˆ๋‹ค.Chapter 1 Introduction 1 1.1. Power Crisis of Conventional CMOS Technology 1 1.2. Tunnel Field-Effect Transistor (TFET) 6 1.3. Feasibility and Challenges of TFET 9 1.4. Scope of Thesis 11 Chapter 2 Device Characterization 13 2.1. SiGe Nanosheet TFET 13 2.2. Device Concept 15 2.3. Calibration Procedure for TCAD simulation 17 2.4. Device Verification with TCAD simulation 21 Chapter 3 Device Fabrication 31 3.1. Fabrication Process Flow 31 3.2. Key Processes for SiGe Nanosheet TFET 33 3.2.1. Key Process 1 : SiGe Nanosheet Formation 34 3.2.2. Key Process 2 : Source/Drain Implantation 41 3.2.3. Key Process 3 : High-ฮบ/Metal gate Formation 43 Chapter 4 Results and Discussion 53 4.1. Measurement Results 53 4.2. Analysis of Device Characteristics 56 4.2.1. Improved Factors to Performance in SiGe Nanosheet TFET 56 4.2.2. Performance Comparison with SiGe Nanosheet MOSFET 62 4.3. Performance Evaluation through Benchmarks 64 4.4. Optimization Plan for SiGe nanosheet TFET 66 4.4.1. Improvement of Quality of Gate Dielectric 66 4.4.2. Optimization of Doping Junction at Source 67 Chapter 5 Conclusion 71 Bibliography 73 Abstract in Korean 81 List of Publications 83Docto

    III-V์กฑ ํ™”ํ•ฉ๋ฌผ ๋ฐ˜๋„์ฒด ํ„ฐ๋„ ์ „๊ณ„ ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ ๊ฐœ๋ฐœ

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    ํ•™์œ„๋…ผ๋ฌธ(๋ฐ•์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ •๋ณด๊ณตํ•™๋ถ€, 2022. 8. ์ตœ์šฐ์˜.๋ฆฌ์†Œ๊ทธ๋ž˜ํ”ผ ๊ธฐ์ˆ ์˜ ๋†€๋ผ์šด ๋ฐœ์ „์€ 10 nm ์ดํ•˜์˜ ๋…ผ๋ฆฌ ํŠธ๋žœ์ง€์Šคํ„ฐ๋ฅผ ์ƒ์šฉํ™”ํ–ˆ๋‹ค. ๊ฒŒ์ดํŠธ ๊ธธ์ด ์Šค์ผ€์ผ๋ง์€ ๋ชจ์ŠคํŽซ (MOSFET)์˜ ์ „๋ ฅ ์†Œ๋น„๋ฅผ ์ค„์ด๊ธฐ ์œ„ํ•œ ๋…ธ๋ ฅ์˜ ํฐ ๋ถ€๋ถ„์„ ์ฐจ์ง€ํ•œ๋‹ค. ๊ทธ๋Ÿฌ๋‚˜ ์ด๋Ÿฌํ•œ ์ ‘๊ทผ ๋ฐฉ์‹์€ ๋ฆฌ์†Œ๊ทธ๋ž˜ํ”ผ์˜ ๋ฌผ๋ฆฌ์  ํ•œ๊ณ„์™€ ๋ˆ„์„ค ์ „๋ฅ˜ ์ œ์–ด์™€ ๊ฐ™์€ ๋ช‡ ๊ฐ€์ง€ ๋ฌธ์ œ์— ์ง๋ฉดํ–ˆ๋‹ค. ๋ชจ์ŠคํŽซ์˜ ๊ทผ๋ณธ์ ์ธ ๋ฌธ์ œ๋Š” ํ˜„์žฌ ์ „์†ก ๋ฉ”์ปค๋‹ˆ์ฆ˜์˜ ํ•œ๊ณ„๋กœ ์ธํ•ด 60 mV/dec ๋ฏธ๋งŒ์˜ ์ž„๊ณ„๊ฐ’ ๊ธฐ์šธ๊ธฐ (SS)์— ๋„๋‹ฌํ•  ์ˆ˜ ์—†๋‹ค๋Š” ๊ฒƒ์ด๋‹ค. Si ํ„ฐ๋„๋ง ์ „๊ณ„ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ (TFET)์˜ ์—ฌ๋Ÿฌ ์—ฐ๊ตฌ์ž๋“ค์ด 60 mV/dec ๋ฏธ๋งŒ์˜ ๊ฒฐ๊ณผ๋ฅผ ๋ณด๊ณ ํ–ˆ์ง€๋งŒ, Si ๋™์ข… ์ ‘ํ•ฉ ํ„ฐ๋„๋ง ์ „๊ณ„ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ๋Š” ๊ฐ„์ ‘ ๋Œ€์—ญ ๊ฐญ ๋ฌผ์งˆ์˜ ํ„ฐ๋„๋ง ํ™•๋ฅ ์ด ๋‚ฎ์•„ ์ „๋ฅ˜์ƒ์œผ๋กœ ๋ถˆ์ถฉ๋ถ„ํ•˜๋‹ค. P-I ์ ‘ํ•ฉ๋ถ€์—์„œ์˜ ํ„ฐ๋„๋ง ํ™•๋ฅ ์€ ํ„ฐ๋„๋ง ์ „๊ณ„ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ์˜ ๋™์ž‘์ „๋ฅ˜์— ์˜ํ–ฅ์„ ๋ฏธ์น˜๊ธฐ ๋•Œ๋ฌธ์— ์ž‘์€ ์ง์ ‘ ๋ฐด๋“œ๊ฐญ์„ ๊ฐ€์ง€๊ณ  ์œ ํšจ์งˆ๋Ÿ‰์ด ๋‚ฎ์€ III-V ํ™”ํ•ฉ๋ฌผ ๋ฐ˜๋„์ฒด๋Š” ์ž„๊ณ„๊ฐ’ ๊ธฐ์šธ๊ธฐ๊ฐ€ 60 mV/dec ๋ฏธ๋งŒ์ธ ๋†’์€ ํ„ฐ๋„๋ง ์ „๋ฅ˜๋ฅผ ๋‹ฌ์„ฑํ•  ์ˆ˜ ์žˆ๋Š” ๊ฐ€์žฅ ์œ ๋งํ•œ ์žฌ๋ฃŒ์ด๋‹ค. ๋˜ํ•œ ๋ฐด๋“œ ์˜คํ”„์…‹์ด ๋‹ค๋ฅธ ์žฌ๋ฃŒ๋ฅผ ์„ ํƒํ•จ์œผ๋กœ์จ, ์Šคํƒœ๊ฑฐ๋“œ ๋˜๋Š” ๋ธŒ๋กœํฐ ๊ฐญ์„ ํ˜•์„ฑํ•จ์œผ๋กœ์จ ํ„ฐ๋„๋ง ์ „๋ฅ˜๋ฅผ ํ˜„์ €ํ•˜๊ฒŒ ์ฆ๊ฐ€์‹œํ‚ฌ ์ˆ˜ ์žˆ๋‹ค. P-I ์ ‘ํ•ฉ๋ถ€์˜ ํ„ฐ๋„๋ง์ด ํ„ฐ๋„ ์ „๊ณ„ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ ์†Œ์ž์˜ ์ „๋ฅ˜ ๊ณต๊ธ‰์›์ด๊ธฐ ๋•Œ๋ฌธ์— ๋งŽ์€ ์—ฐ๊ตฌ์ž๋“ค์ด ๋ถ„์ž๋น” ์—ํ”ผํƒ์‹œ (MBE) ๋ฐฉ์‹์œผ๋กœ ์„ฑ์žฅํ•œ pํ˜• ๋„ํ•‘ ๋†๋„๊ฐ€ ๋†’์€ III-V ์›จ์ดํผ๋กœ ์ œ์กฐ๋œ ํ„ฐ๋„ ์ „๊ณ„ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ์˜ ์„ฑ๋Šฅ์„ ๋ณด๊ณ ํ•ด์™”๋‹ค. ๊ทธ๋Ÿฌ๋‚˜ ๋†’์€ ๋„ํ•‘ ๋†๋„์™€ ๊ฐ€ํŒŒ๋ฅธ ๋„ํŽ€ํŠธ ํ”„๋กœํŒŒ์ผ์„ ๊ฐ–๋Š” pํ˜• InGaAs๋ฅผ ์„ฑ์žฅํ•˜๊ธฐ๊ฐ€ ๊นŒ๋‹ค๋กญ๊ธฐ ๋•Œ๋ฌธ์— ๊ธˆ์†-์œ ๊ธฐ ํ™”ํ•™ ๊ธฐ์ƒ ์ฆ์ฐฉ (MOCVD) ์„ฑ์žฅ ์—ํ”ผํƒ์…œ ์ธต์—์„œ ์ œ์กฐ๋œ InGaAs TFET ์†Œ์ž๋Š” ๊ฑฐ์˜ ๋ณด๊ณ ๋˜์ง€ ์•Š์•˜๋‹ค. ์ด์— ๋”ฐ๋ผ ๋ณธ ์—ฐ๊ตฌ๋Š” TFET ์†Œ์ž ์ œ์ž‘์„ ์œ„ํ•œ ๊ณ ํ’ˆ์งˆ ์—ํ”ผํƒ์…œ ์ธต์„ ์„ฑ์žฅ์‹œํ‚ค๊ธฐ ์œ„ํ•œ MOCVD ์„ฑ์žฅ ๊ธฐ์ˆ ์„ ์„ ๋ณด์ธ๋‹ค. ์ข…๋ž˜์˜ TFET ์†Œ์ž์— ๋Œ€ํ•ด์„œ๋Š” ๋™์ข… ์ ‘ํ•ฉ p-i-n InGaAs ์—ํ”ผํƒ์…œ์ธต์„ ์„ฑ์žฅ์‹œํ‚ค๊ณ , p++-Ge/i-InGaAs/n+-InAs ๋‚˜๋…ธ์„ ์„ ์„ฑ์žฅ์‹œ์ผœ TFET ์†Œ์ž ์„ฑ๋Šฅ ํ–ฅ์ƒ ๊ฐ€๋Šฅ์„ฑ์„ ํ™•์ธํ•˜์˜€๋‹ค. MOCVD์— ์˜ํ•ด ์„ฑ์žฅํ•œ ์—ํ”ผํƒ์‹œ ์ธต์—์„œ ์ œ์กฐ๋œ TFET ์†Œ์ž์˜ ์ž ์žฌ์„ฑ์„ ํ™•์ธํ•˜๊ธฐ ์œ„ํ•ด ํ‰ํŒ๊ณผ ๋‚˜๋…ธ์„  ์—ํ”ผํƒ์…œ ์ธต์—์„œ ์ œ์ž‘๋œ TFET ์†Œ์ž์˜ ์„ฑ๋Šฅ์ด ํ™•์ธ๋˜์—ˆ๋‹ค. MOCVD ๋ฐฉ๋ฒ•์„ ์ด์šฉํ•˜์—ฌ ๊ณ ํ’ˆ์งˆ์˜ ์—ํ”ผํƒ์…œ ์ธต์ด ์„ฑ์žฅ๋˜์—ˆ๋‹ค. MBE์— ๋น„ํ•ด ๊ฐ€์„ฑ๋น„, ๋†’์€ ์ฒ˜๋ฆฌ๋Ÿ‰, ์šฐ์ˆ˜ํ•œ ๊ฒฐ์ • ํ’ˆ์งˆ์ด MOCVD์˜ ๊ฐ€์žฅ ํฐ ์žฅ์ ์ด๋‹ค. ์ด์— ์—ฌ๋Ÿฌ ์„ฑ์žฅ ์กฐ๊ฑด์„ ๋ณ€ํ™”์‹œํ‚ค๋ฉด์„œ InP (001) ๊ธฐํŒ ์œ„๋กœ InGaAs ํ•„๋ฆ„์ธต์˜ ์„ฑ์žฅ์ด ์—ฐ๊ตฌ๋˜์—ˆ๋‹ค. ์†Œ์Šค ์œ ๋Ÿ‰, ์˜จ๋„ ๋ฐ V/III ๋น„์œจ์ด ์„ฑ์žฅ๋œ InGaAs ํ•„๋ฆ„์ธต์˜ ํ’ˆ์งˆ์— ๋ผ์น˜๋Š” ์˜ํ–ฅ์ด ์—ฐ๊ตฌ๋˜์—ˆ๋‹ค. ๋˜ํ•œ MOCVD InGaAs ์„ฑ์žฅ ๊ธฐ์ˆ ์—์„œ nํ˜• ๋ฐ pํ˜• ๋„ํŽ€ํŠธ์˜ ๋†๋„๋ฅผ ๋†’์ด๋Š” ๊ฒƒ๊ณผ ๋„ํŽ€ํŠธ ํ”„๋กœํŒŒ์ผ์„ ๊ฐ€ํŒŒ๋ฅด๊ฒŒ ํ•˜๋Š” ๊ฒƒ์ด ๋„์ „์ ์ด๋ฏ€๋กœ ํƒ„์†Œ ๋ฐ ํ…”๋ฃจ๋ฅจ ๋„ํ•‘์„ ํ†ตํ•ด ๊ฐ€ํŒŒ๋ฅธ ๋„ํŽ€ํŠธ ํ”„๋กœํŒŒ์ผ์„ ๋ณด์ด๋Š” ๊ณ ๋†๋„์˜ pํ˜• ๋ฐ nํ˜• InGaAs์ธต์„ ์„ฑ์žฅํ•˜์˜€๋‹ค. ์„ฑ์žฅ๋œ ์—ํ”ผํƒ์…œ ํ•„๋ฆ„์ธต์€ TFET ์†Œ์ž๋ฅผ ์ œ์ž‘ํ•˜์—ฌ ํ‰๊ฐ€ํ•˜์˜€๋‹ค. TFET ์†Œ์ž ์ œ์ž‘ ์ „์— ์šฐ์„  TFET ์†Œ์ž์˜ ์ฑ„๋„ ๊ธธ์ด๊ฐ€ ์ „๊ธฐ์  ์‹œ๋ฎฌ๋ ˆ์ด์…˜ ๊ฒฐ๊ณผ์— ์˜ํ•ด ์„ ํƒ๋˜์—ˆ๋‹ค. MOCVD๋ฅผ ์ด์šฉํ•˜์—ฌ ๋„ํ•‘ ํ”„๋กœํŒŒ์ผ์ด ๊ฐ€ํŒŒ๋ฅธ ๊ณ ํ’ˆ์งˆ์˜ ์ˆ˜์ง p-i-n ์—ํ”ผํ…์…œ ๊ตฌ์กฐ๊ฐ€ ํ•œ๋ฒˆ์— ์„ฑ์žฅ๋˜์—ˆ๋‹ค. ์—ํ”ผํƒ์…œ ์„ฑ์žฅ ํ›„์— TFET ์†Œ์ž๋Š” ์ˆ˜์ง ๋ฐฉํ–ฅ์˜ ์Šต์‹ ์‹๊ฐ์„ ํ†ตํ•ด ์ œ์ž‘๋˜์—ˆ๋‹ค. ์˜ด (Ohmic) ๊ณต์ •๊ณผ ์—์–ด๋ธŒ๋ฆฟ์ง€ ๊ณต์ •๋„ ์†Œ์ž ์ œ์ž‘์„ ์œ„ํ•ด ์ตœ์ ํ™”๋˜์—ˆ๋‹ค. Pํ˜• ๋„ํ•‘ ๋†๋„์— ๋Œ€ํ•œ ์˜ํ–ฅ๊ณผ MOCVD ์„ฑ์žฅ ์ค‘์— ์ƒ๊ธด ์ „์œ„์— ๋Œ€ํ•œ ์˜ํ–ฅ์ด TFET ์„ฑ๋Šฅ์„ ํ†ตํ•˜์—ฌ ํ™•์ธ๋˜์—ˆ๋‹ค. ์ œ์กฐ๋œ TFET ์†Œ์ž๋Š” 60 mV/dec์— ๊ฐ€๊นŒ์šด SS์™€ ๊ดœ์ฐฎ์€ ์˜จ/์˜คํ”„ ์ „๋ฅ˜ ๋น„์œจ์„ ๋ณด์—ฌ์ฃผ์—ˆ๋Š”๋ฐ, ์ด๋Š” ์ตœ์ดˆ๋กœ ๋ณด๊ณ ๋˜๋Š” MBE์—์„œ ์„ฑ์žฅ๋œ ์›จ์ดํผ์—์„œ ๋งŒ๋“ค์–ด์ง„ TFET ์†Œ์ž์™€ ๋น„๊ตํ•  ์ˆ˜ ์žˆ๋Š” ์†Œ์ž์ด๋‹ค. ์ด ๊ฒฐ๊ณผ๋Š” ๊ณ ํ’ˆ์งˆ์˜ MOCVD๋กœ ์„ฑ์žฅํ•œ III-V TFET ์†Œ์ž์˜ ์–‘์‚ฐ ๊ฐ€๋Šฅ์„ฑ์„ ๋ณด์—ฌ์ค€๋‹ค. ์ด ์—ฐ๊ตฌ์˜ ๋‹ค์Œ ๋ถ€๋ถ„์€ ๋‚˜๋…ธ์„  TFET ์ œ์ž‘์ด๋‹ค. ์ „์ž์†Œ์ž ์ œ์ž‘์„ ์œ„ํ•œ III-V ๋‚˜๋…ธ์„  ์„ฑ์žฅ์—๋Š” ๋ช‡ ๊ฐ€์ง€ ์žฅ์ ์ด ์žˆ๋‹ค. ๋‹ค์–‘ํ•œ ์ข…๋ฅ˜์˜ ์›จ์ดํผ์— ๋‹ค์–‘ํ•œ ํŠน์„ฑ์„ ๊ฐ€์ง€๋Š” ํ—คํ…Œ๋กœ ๊ตฌ์กฐ๋ฅผ ํ˜•์„ฑํ•  ์ˆ˜ ์žˆ๋‹ค๋Š” ๊ฒƒ์ด ํฐ ์žฅ์ ์ด๋‹ค. ์ถฉ๋ถ„ํžˆ ์ž‘์€ ์ง๊ฒฝ์œผ๋กœ ์„ฑ์žฅ๋œ ๋‚˜๋…ธ์„ ์€ ์›จ์ดํผ์™€ ๋‹ค๋ฅธ ๊ฒฉ์ž ์ƒ์ˆ˜๋ฅผ ๊ฐ€์ง€๋”๋ผ๋„ ์ „์œ„ ์—†๋Š” ๊ณ„๋ฉด์„ ๊ฐ€์ง„๋‹ค. ๋‹ค์–‘ํ•œ ์œ ํ˜•์˜ ๋ฐด๋“œ ์ •๋ ฌ์ด ๋งŒ๋“ค์–ด์งˆ ์ˆ˜ ์žˆ์œผ๋ฉฐ, ์ด๋Š” TFET์˜ ํ„ฐ๋„๋ง ์ •๋ฅ˜๋ฅผ ์ฆ๊ฐ€์‹œํ‚ค๋Š” ๋ฐ์— ์žˆ์–ด ์ค‘์š”ํ•œ ์š”์†Œ์ด๋‹ค. ๋˜ํ•œ ์ง๊ฒฝ์ด ์ž‘์€ ๋‚˜๋…ธ์„ ์€ ์นฉ์œผ๋กœ ์ œ์ž‘๋˜์—ˆ์„ ๋•Œ ๋” ๋‚˜์€ ์†Œ์ž ๋ฐ€๋„, ํ–ฅ์ƒ๋œ ๊ฒŒ์ดํŠธ ์ œ์–ด์„ฑ, ์„ฑ์žฅ ์‹œ๊ฐ„ ๋‹จ์ถ•์„ ํ†ตํ•œ ์ฒ˜๋ฆฌ๋Ÿ‰ ํ–ฅ์ƒ์ด ๊ฐ€๋Šฅํ•˜๋‹ค. InGaAs ๋‚˜๋…ธ์„ ์€ ์„ ํƒ์  ์˜์—ญ ์„ฑ์žฅ๋ฒ• (SAG) ์„ฑ์žฅ๋˜์—ˆ๋‹ค. ํ•˜๋“œ๋งˆ์Šคํฌ ์ธต์œผ๋กœ์„œ InP (111)B ๋ฐ Ge (111) ์›จ์ดํผ์— SiO2 ์ธต์ด ์ฆ์ฐฉ ๋˜์—ˆ๋‹ค. ์„ฑ์žฅ ๋ชจ๋“œ๊ฐ€ ๋‹ค๋ฅด๊ธฐ ๋•Œ๋ฌธ์— InGaAs ํ‰ํŒ ํ•„๋ฆ„์ธต ์„ฑ์žฅ๊ณผ๋Š” ํฌ๊ฒŒ ๋‹ค๋ฅธ ์„ฑ์žฅ ์กฐ๊ฑด์„ ํ…Œ์ŠคํŠธํ•˜์˜€๋‹ค. ๋‚˜๋…ธ์„ ์˜ ์„ ํƒ์  ์„ฑ์žฅ์€ ์˜จ๋„, V/III ๋น„์œจ ๋ฐ ์†Œ์Šค ์œ ๋Ÿ‰์„ ์ตœ์ ํ™”ํ•˜์—ฌ ํ™•์ธํ•˜์˜€๋‹ค. ๊ทธ ๊ฒฐ๊ณผ InP (111)B์™€ Ge (111) ์›จ์ดํผ์—์„œ InAs์™€ InGaAs ๋‚˜๋…ธ์„ ์„ ์„ฑ๊ณต์ ์œผ๋กœ ์„ฑ์žฅ์‹œ์ผฐ๋‹ค. Pํ˜• ๋ฌผ์งˆ๋กœ๋Š” p++๋„ํ•‘๋œ Ge (111) ์›จ์ดํผ๋ฅผ ์‚ฌ์šฉํ•˜์˜€๋‹ค. ์ธํŠธ๋ฆฐ์‹ InGaAs์™€ InAs ๋‚˜๋…ธ์„ ์ด ๊ทธ ์œ„์— ์„ ํƒ์ ์œผ๋กœ ์„ฑ์žฅ๋˜์—ˆ๋‹ค. ๋งˆ์ง€๋ง‰์œผ๋กœ ์‹ค๋ฆฌ์ฝ˜ ๋„ํŽ€ํŠธ๋ฅผ ๊ฐ€์ง„ nํ˜• InAs ๋‚˜๋…ธ์„ ์ด ํ›„์†์ ์œผ๋กœ ์„ฑ์žฅ๋˜์—ˆ๋‹ค. ์„ฑ์žฅ๋œ ๋‚˜๋…ธ์„ ์€ ์ˆ˜์ง ๋‚˜๋…ธ์„  TFET์„ ์ œ์ž‘ํ•˜์—ฌ ํ‰๊ฐ€๋˜์—ˆ๋‹ค. ๋†’์€ ๋‹จ๊ณ„ ์ปค๋ฒ„๋ฆฌ์ง€์™€ ์–‘ํ˜ธํ•œ ์ธํ„ฐํŽ˜์ด์Šค ์ƒํƒœ ๋ฐ€๋„๋ฅผ ์œ„ํ•˜์—ฌ ALD HfO2 ๋ฐ ALD TiN ๊ณต์ •๊ณผ์ •์ด ์ตœ์ ํ™”๋˜์—ˆ๋‹ค. ๊ฐœ๋ฐœ๋œ ALD ๊ณต์ •์„ ์ ์šฉํ•จ์œผ๋กœ์จ ์ˆ˜์งํ˜• ๋‚˜๋…ธ์„  Ge/InGaAs ํ—คํ…Œ๋กœ ์ ‘ํ•ฉ TFET์˜ ๋™์ž‘์ด ์„ฑ๊ณต์ ์œผ๋กœ ํ™•์ธ๋˜์—ˆ๋‹ค.The remarkable development of lithography technology commercialized the sub-10 nm logic transistors. Gate length scaling is a large portion of the effort to reduce the power consumption of metal-oxide-semiconductor field-effect transistors (MOSFETs). However, this approach faces several problems, such as the physical limitation of lithography and leakage current control. The fundamental problem of MOSFETs is that they cannot reach subthreshold-slope (SS) below 60 mV/dec due to their current transport mechanism. Several researchers of Si tunneling field-effect transistors (TFETs) reported sub-60 mV/dec, but Si homo-junction TFETs show insufficient on-current due to the poor tunneling probability of indirect-band gap materials. As tunneling probability at the p-i junction influences the on-current of TFETs, III-V compound semiconductors, which have a direct small band gap and low effective masses, are the most promising materials to achieve high tunneling current with SS below 60 mV/dec. Also, the tunneling current can be remarkably increased by forming a staggered or broken gap by choosing materials with different band offsets. Since the tunneling at a p-i junction is the current source of TFET devices, many researchers have reported the performance of TFETs fabricated from III-V wafers with high p-type doping concentration grown by the molecular beam epitaxy (MBE) method. However, very few InGaAs TFET devices fabricated on MOCVD-grown epitaxial layers have been reported due to the challenging techniques for achieving p-type InGaAs with high doping concentration and steep dopant profile. Accordingly, this work demonstrates the metal-organic chemical vapor deposition (MOCVD) growth techniques to grow a high-quality epitaxial layer for TFET device fabrication. Homo-junction p-i-n InGaAs epitaxial layers were grown for conventional TFET devices, and hetero-junction p++-Ge/i-InGaAs/n+-InAs nanowires were grown to confirm the possibility of boosting the TFET device performance. The TFET device performance at both epitaxial layers was characterized to confirm the potential of TFET devices fabricated on the epitaxy layers grown by the MOCVD method. The high-quality epitaxial layers were grown using the MOCVD method. Compared to the MBE method, cost-effectiveness, high throughput, and excellent crystal quality are the significant advantages of the MOCVD method. The growth of InGaAs film layers on InP (001) substrate with several growth conditions was studied. The effects of source flow rate, temperature, and V/III ratio on the quality of grown InGaAs film layers were studied. As the high-concentration and steep dopant profile of n-type and p-type dopants are challenging in MOCVD InGaAs growth technique, carbon and tellurium doping techniques were introduced to achieve highly-doped p-type and n-type InGaAs layer with steep dopant profile. The grown epitaxial film layers were evaluated by fabricating the TFET device. Before the TFET device fabrication, the dimensions of the TFET device were selected by electrical simulation results of TFET devices with different structures. For TFET device fabrication, a high-quality vertical p-i-n epitaxial structure with a steep doping profile was successively formed by MOCVD. After epitaxial growth, the TFET devices were fabricated by the vertical top-down wet etching method. The ohmic process and air-bridge process were also optimized for device fabrication. The effect of p-type doping concentration and the dislocations formed during MOCVD growth was confirmed by TFET performance. The fabricated TFET devices showed SS of near-60 mV/dec and sound on/off current ratio, which was by far the first reported device comparable to TFET devices fabricated on the MBE-grown wafers. This result represents the possible mass-production of high-quality MOCVD-grown III-V TFET devices. The next part of this study is nanowire TFET fabrication. The growth of III-V nanowires for electronic device fabrication has several advantages. The significant advantage is that hetero-structures with various characteristics can be formed on various wafers. The nanowires grown by a sufficiently small diameter show a dislocation-free interface even if nanowires have a different lattice constant compared to the wafer. Various types of band-alignment can be formed, and this is a crucial factor in boosting the tunneling current of TFETs. Also, nanowires with a small diameter show better device density in a chip, improved gate controllability, and enhanced throughput by reducing growth time. The InGaAs nanowires were grown by the selective area growth (SAG) method. As a hard-mask layer, a SiO2 layer was deposited on InP (111)B and Ge (111) wafers. Growth conditions far different from InGaAs film layer growth were tested due to the different growth modes. Selective growth of nanowires was identified by optimizing temperature, V/III ratio, and source flow rate. As a result, InAs and InGaAs nanowires were successfully grown on InP (111)B and Ge (111) wafers. For p-type material, the p++-doped Ge (111) wafer was used. The intrinsic InGaAs and InAs nanowires were selectively grown on the patterned substrate. Finally, n-type InAs nanowires with silicon dopant were grown subsequently. The grown nanowires were evaluated by fabricating the vertical nanowire TFETs. ALD HfO2 and ALD TiN processes were optimized for high step coverage and good interface state density. By applying the developed ALD processes, a successful demonstration of vertical nanowire Ge/InGaAs hetero-junction TFET was observed.Contents List of Tables List of Figures Chapter 1. Introduction 1 1.1. Backgrounds 1 1.2. III-V TFETs for Low Power Device 5 1.3. Epitaxy of III-V Materials 12 1.4. Research Aims 17 1.5. References 20 Chapter 2. Epitaxial Growth of InGaAs on InP (001) Substrate 24 2.1. Introduction 24 2.2. Temperature Dependent Properties of Intrinsic-InGaAs on InP (001) Substrate 33 2.3. In-situ Doping Properties of InGaAs on InP (001) Substrate 37 2.4. Conclusion 51 2.5. References 52 Chapter 3. Demonstration of TFET Device Fabricated on InGaAs-on-InP (001) Substrate 56 3.1. Introduction 56 3.2. Simulation of Basic Operations of TFET Device 60 3.3. Process Optimization of TFET Fabrication 68 3.4. Process Flow 74 3.5. Characterization of TFETs Fabricated on MBE-grown and MOCVD-grown Wafers 78 3.6. Conclusion 96 3.7. References 97 Chapter 4. Selective Area Growth of In(Ga)As Nanowires 101 4.1. Introduction 101 4.2. Process Flow of Nanowire Growth 108 4.3. Impact of Different Growth Variables on the Growth of InAs Nanowires 113 4.4. Impact of Different Growth Variables on the Growth of InGaAs Nanowires 127 4.5. Conclusion 144 4.6. References 146 Chapter 5. Demonstration of Vertical Nanowire TFET 149 5.1. Introduction 149 5.2. Optimization of ALD HfO2 High-k Stack 152 5.3. Optimization of ALD TiN Gate Metal 169 5.4. Detailed Demonstration of Vertical Nanowire TFET Fabrication Processes 182 5.5. Characterization of Fabricated Vertical Nanowire TFETs 196 5.6. Conclusion 203 5.7. References 205 Chapter 6. Conclusions and Outlook 209 6.1. Conclusions 209 6.2. Outlook 211 Appendix. 213 A. n+-InAs Nanowire Doping Concentration Evaluation by TLM Method 213 B. n+-InAs Nanowire Doping Concentration Evaluation by C-V Method 219 C. References 205 Abstract in Korean 226 Research Achievements 230๋ฐ•

    Electrical Characterisation of III-V Nanowire MOSFETs

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    The ever increasing demand for faster and more energy-efficient electricalcomputation and communication presents severe challenges for the semiconductor industry and particularly for the metal-oxidesemiconductorfield-effect transistor (MOSFET), which is the workhorse of modern electronics. III-V materials exhibit higher carrier mobilities than the most commonly used MOSFET material Si so that the realisation of III-V MOSFETs can enable higher operation speeds and lower drive voltages than that which is possible in Si electronics. A lowering of the transistor drive voltage can be further facilitated by employing gate-all-around nanowire geometries or novel operation principles. However, III-V materials bring about their own challenges related to material quality and to the quality of the gate oxide on top of a III-V MOSFET channel.This thesis presents detailed electrical characterisations of two types of (vertical) III-V nanowire transistors: MOSFETs based on conventional thermionic emission; and Tunnel FETs, which utilise quantum-mechanical tunnelling instead to control the device current and reach inverse subthreshold slopes below the thermal limit of 60 mV/decade. Transistor characterisations span over fourteen orders of magnitude in frequency/time constants and temperatures from 11 K to 370 K.The first part of the thesis focusses on the characterisation of electrically active material defects (โ€˜trapsโ€™) related to the gate stack. Low-frequency noise measurements yielded border trap densities of 10^18 to 10^20 cm^-3 eV^-1 and hysteresis measurements yielded effective trap densities โ€“ projected to theoxide/semiconductor interface โ€“ of 2x10^12 to 3x10^13 cm^-2 eV^-1. Random telegraph noise measurements revealed that individual oxide traps can locally shift the channel energy bands by a few millielectronvolts and that such defects can be located at energies from inside the semiconductor band gap all the way into the conduction band.Small-signal radio frequency (RF) measurements revealed that parts of the wide oxide trap distribution can still interact with carriers in the MOSFET channel at gigahertz frequencies. This causes frequency hystereses in the small-signal transconductance and capacitances and can decrease the RF gains by a few decibels. A comprehensive small-signal model was developed, which takes into account these dispersions, and the model was applied to guide improvements of the physical structure of vertical RF MOSFETs. This resulted in values for the cutoff frequency fT and the maximum oscillation frequency fmax of about 150 GHz in vertical III-V nanowire MOSFETs.Bias temperature instability measurements and the integration of (lateral) III-V nanowire MOSFETs in a back end of line process were carried out as complements to the main focus of this thesis. The results of this thesis provide a broad perspective of the properties of gate oxide traps and of the RF performance of III-V nanowire transistors and can act as guidelines for further improvement and finally the integration of III-V nanowire MOSFETs in circuits

    A review of selected topics in physics based modeling for tunnel field-effect transistors

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    The research field on tunnel-FETs (TFETs) has been rapidly developing in the last ten years, driven by the quest for a new electronic switch operating at a supply voltage well below 1 V and thus delivering substantial improvements in the energy efficiency of integrated circuits. This paper reviews several aspects related to physics based modeling in TFETs, and shows how the description of these transistors implies a remarkable innovation and poses new challenges compared to conventional MOSFETs. A hierarchy of numerical models exist for TFETs covering a wide range of predictive capabilities and computational complexities. We start by reviewing seminal contributions on direct and indirect band-to-band tunneling (BTBT) modeling in semiconductors, from which most TCAD models have been actually derived. Then we move to the features and limitations of TCAD models themselves and to the discussion of what we define non-self-consistent quantum models, where BTBT is computed with rigorous quantum-mechanical models starting from frozen potential profiles and closed-boundary Schr\uf6dinger equation problems. We will then address models that solve the open-boundary Schr\uf6dinger equation problem, based either on the non-equilibrium Green's function NEGF or on the quantum-transmitting-boundary formalism, and show how the computational burden of these models may vary in a wide range depending on the Hamiltonian employed in the calculations. A specific section is devoted to TFETs based on 2D crystals and van der Waals hetero-structures. The main goal of this paper is to provide the reader with an introduction to the most important physics based models for TFETs, and with a possible guidance to the wide and rapidly developing literature in this exciting research field

    Digital and analog TFET circuits: Design and benchmark

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    In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10 nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDDlower than 0.4 V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions

    Vertical III-V Nanowire Transistors for Low-Power Electronics

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    Power dissipation has been the major challenge in the downscaling of transistor technology. Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) have struggled to keep a low power consumption while still maintaining a high performance due to the low carrier mobilities of Si but also due to their inherent minimum inverse subthreshold slope (S โ‰ฅ 60 mV/dec) which is limited by thermionic emission. This thesis work studied the capabilities and limitations of III-V based vertical nanowire n-type Tunneling Field-Effect Transistor (TFET) and p-type MOSFET (PMOS). InAs/InGaAsSb/GaSb heterojunction was employed in the whole study. The main focus was to understand the influence of the device fabrication processes and the structural factors of the nanowires such as band alignment, composition and doping on the electrical performance of the TFET. Optimizations of the device processes including spacer technology improvement, Equivalent Oxide Thickness (EOT) downscaling, and gate underlap/overlap were explored utilizing structural characterizations. Systematic fine tuning of the band alignment of the tunnel junction resultedin achieving the best performing sub-40 mV/dec TFETs with S = 32 mV/decand ION = 4ฮผA/ฮผm for IOFF = 1 nA/ฮผm at VDS = 0.3 V. The suitability of employing TFET for electronic applications at cryogenic temperatures has been explored utilizing experimental device data. The impact of the choice of heterostructure and dopant incorporation were investigated to identify the optimum operating temperature and voltage in different temperature regimes. A novel gate last process self-aligning the gate and drain contacts to the intrinsic and doped segments, respectively was developed for vertical InGaAsSb-GaAsSb core-shell nanowire transistors leading to the first sub-100 mV/dec PMOS with S = 75 mV/dec, significant ION/ IOFF = 104 and IMIN < 1 nA/ฮผm at VDS = -0.5 V

    Digital and analog TFET circuits: Design and benchmark

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    In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10 nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDDlower than 0.4 V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions

    Vertical III-V Nanowire Transistors for Low-Power Logic and Reconfigurable Applications

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    With rapid increase in energy consumption of electronics used in our daily life, the building blocks โ€” transistors โ€” need to work in a way that has high energy efficiency and functional density to meet the demand of further scaling. III-V channel combined with vertical nanowire gate-all-around (GAA) device architecture is a promising alternative to conventional Si transistors due to its excellent electrical properties in the channel and electrostatic control across the gate oxide in addition to reduced footprint. Based on this platform, two major objectives of this thesis are included: 1) to improve the performance of III-V p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) and tunnel FETs (TFETs) for low-power digital applications; 2) to integrate HfO2-based ferroelectric gate onto III-V FETs (FeFETs) and TFETs (ferro-TFETs) to enable reconfigurable operation for high functional density.The key bottleneck for all-III-V CMOS is its p-type MOSFETs (p-FETs) which are mainly made of GaSb or InGaSb. Rich surface states of III-Sb materials not only lead to decreased effective channel mobility due to more scattering, but also deteriorate the electrostatics. In this thesis, several approaches to improve p-FET performance have been explored. One strategy is to enhance the hole mobility by introducing compressive strain into III-Sb channel. For the first time, a high and uniform compressive strain near 1% along the transport direction has been achieved in downscaled GaSb nanowires by growing and engineering GaSb-GaAsSb core-shell structure, aiming for potential hole mobility enhancement. In addition, surface passivation using digital etch has been developed to improve the electrostatics with subthreshold swing (SS) down to 107 mV/dec. Moreover, the on-state performance including on-current (Ion) and transconductance (gm) have been enhanced by โˆผ50% using annealing with H2-based forming gas. Lastly, a novel p-FET structure with (In)GaAsSb channel has been developed and further improved off-state performance with SS = 71 mV/dec, which is the lowest value among all reported III-V p-FETs.Despite subthermionic operation, TFETs usually suffer from low drive current as well as the current operating below 60 mV/dec (I60). The second focus of this thesis is to fine-tune the InAs/(In)GaAsSb heterostructure tunnel junction and the doping in the source segment during epitaxy. As a result, a substantially increased I60 (>1 ยตA/ยตm) and Ion up to 40 ยตA/ยตm at source-drain bias of 0.5 V have been achieved, reaching a record compared to other reported TFETs.Finally, emerging ferroelectric oxide based on Zr-doped HfO2 (HZO) has been successfully integrated onto III-V vertical nanowire transistors to form FeFETs and ferro-TFETs with GAA architecture. The corresponding electrical performance and reliability have been carefully characterized with both DC and pulsed I-V measurements. The unique band-to-band tunneling in InAs/(In)GaAsSb/GaSb heterostructure TFET creates an ultrashort effective channel, leading to detection of localized potential variation induced by single domains and defects in nanoscale ferroelectric HZO without physical gate-length scaling. By introducing gate/source overlap structure in the ferro-TFET, non-volatile reconfigurable signal modulation with multiple modes including signal transmission, phase shift, frequency doubling, and mixing has been achieved in a single device with low drive voltage and only โˆผ0.01 ยตm2 footprint, thus increasing both functional density andenergy efficiency
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