Dominant Channel Estimation via MIPS for Large-Scale Antenna Systems with One-Bit ADCs

In large-scale antenna systems, using one-bit analog-to-digital converters (ADCs) has recently become important since they offer significant reductions in both power and cost. However, in contrast to high-resolution ADCs, the coarse quantization of one-bit ADCs results in an irreversible loss of information. In the context of channel estimation, studies have been developed extensively to combat the performance loss incurred by one-bit ADCs. Furthermore, in the field of array signal processing, direction-of-arrival (DOA) estimation combined with one-bit ADCs has gained growing interests recently to minimize the estimation error. In this paper, a channel estimator is proposed for one-bit ADCs where the channels are characterized by their angular geometries, e.g., uniform linear arrays (ULAs). The goal is to estimate the dominant channel among multiple paths. The proposed channel estimator first finds the DOA estimate using the maximum inner product search (MIPS). Then, the channel fading coefficient is estimated using the concavity of the log-likelihood function. The limit inherent in one-bit ADCs is also investigated, which results from the loss of magnitude information.Comment: to appear in GLOBECOM 2018, Abu Dhabi, UA

SVM-Based Channel Estimation and Data Detection for One-Bit Massive MIMO systems

The use of low-resolution Analog-to-Digital Converters (ADCs) is a practical solution for reducing cost and power consumption for massive Multiple-Input-Multiple-Output (MIMO) systems. However, the severe nonlinearity of low-resolution ADCs causes significant distortions in the received signals and makes the channel estimation and data detection tasks much more challenging. In this paper, we show how Support Vector Machine (SVM), a well-known supervised-learning technique in machine learning, can be exploited to provide efficient and robust channel estimation and data detection in massive MIMO systems with one-bit ADCs. First, the problem of channel estimation for uncorrelated channels is formulated as a conventional SVM problem. The objective function of this SVM problem is then modified for estimating spatially correlated channels. Next, a two-stage detection algorithm is proposed where SVM is further exploited in the first stage. The performance of the proposed data detection method is very close to that of Maximum-Likelihood (ML) data detection when the channel is perfectly known. We also propose an SVM-based joint Channel Estimation and Data Detection (CE-DD) method, which makes use of both the to-be-decoded data vectors and the pilot data vectors to improve the estimation and detection performance. Finally, an extension of the proposed methods to OFDM systems with frequency-selective fading channels is presented. Simulation results show that the proposed methods are efficient and robust, and also outperform existing ones

The Design of a Low-Cost Traffic Calming Radar - Development of a radar solution intended to demonstrate proof of concept

This study aimed to develop a radar solution that would aid the traffic calming efforts of the CSIR business campus. The Institute of Transportation Engineers defined traffic calming as "The combination of mainly physical measures that reduce the negative effects of motor vehicle use." Radar-based solutions have been proven to help reduce the speeds of motorists in areas with speed restrictions. Unfortunately, these solutions are expensive and difficult to import. Thus, this dissertation's main focus is to produce a detailed blueprint of a radar-based solution, with technical specifications that are similar to those of commercial and experimental systems at relatively low-cost. With the above mindset, the project was initiated with the user requirements being stated. Then a detailed study of current experimental and commercial radar-based traffic calming systems followed. Thereafter, the technical and non-technical requirements were derived from user requirements, and the technical specifications obtained from the literature study. A review of fundamental radar and signal processing principles was initiated to give background knowledge for the design and simulation process. Consequently, a detailed design of the system's functional components was conceptualized, which included the hardware, software, and electrical aspects of the system as well as the enclosure design. With the detailed design in mind, a data-collection system was built. The data-collection system was built to verify whether the technical specifications, which relate to the detection performance and the velocity accuracy of the proposed radar design, were met. This was done to save on buying all the components of the proposed system while proving the design's technical feasibility. The data-collection system consisted of a radar sensor, an Analogue to Digital Converter (ADC), and a laptop computer. The radar sensor was a k-band, Continuous Wave (CW) transceiver, which provided I/Q demodulated data with beat frequencies ranging from DC to 50 kHz. The ADC is an 8-bit Picoscope 2206B portable oscilloscope, capable of sampling frequencies of up to 50 MHz. The target detection and the velocity estimation algorithms were executed on a Samsung Series 7 Chronos laptop. Preliminary experiments enabled the approximation of the noise intensity of the scene in which the radar would be placed. These noise intensity values enabled the relationship between the Signal to Noise Ratio (SNR) and the velocity error to be modelled at specific ranges from the radar, which led to a series of experiments that verified the prototypes' ability to accurately detect and estimate the vehicle speed at distances of up to 40 meters from the radar. The cell-averaging constant false alarm rate (CA-CFAR) detector was chosen as an optimum detector for this application, and parameters that produced the best results were found to be 50 reference cells and 12 guard cells. The detection rate was found to be 100% for all coherent processing intervals (CPIs) tested. The prototype was able to detect vehicle speeds that ranged from 2 km/h up to 60 km/h with an uncertainty of ±0.415 km/h, ±0.276 km/h, and ±0.156 km/h using a CPI of 0.0128 s, 0.256 s, and 0.0512 s respectively. The optimal CPI was found to be 0.0512 s, as it had the lowest mean velocity uncertainty, and it produced the largest first detection SNR of the CPIs tested. These findings were crucial for the feasibility of manufacturing a low-cost traffic calming solution for the South African market

A Novel Power-Efficient Wireless Multi-channel Recording System for the Telemonitoring of Electroencephalography (EEG)

This research introduces the development of a novel EEG recording system that is modular, batteryless, and wireless (untethered) with the supporting theoretical foundation in wireless communications and related design elements and circuitry. Its modular construct overcomes the EEG scaling problem and makes it easier for reconfiguring the hardware design in terms of the number and placement of electrodes and type of standard EEG system contemplated for use. In this development, portability, lightweight, and applicability to other clinical applications that rely on EEG data are sought. Due to printer tolerance, the 3D printed cap consists of 61 electrode placements. This recording capacity can however extend from 21 (as in the international 10-20 systems) up to 61 EEG channels at sample rates ranging from 250 to 1000 Hz and the transfer of the raw EEG signal using a standard allocated frequency as a data carrier. The main objectives of this dissertation are to (1) eliminate the need for heavy mounted batteries, (2) overcome the requirement for bulky power systems, and (3) avoid the use of data cables to untether the EEG system from the subject for a more practical and less restrictive setting. Unpredictability and temporal variations of the EEG input make developing a battery-free and cable-free EEG reading device challenging. Professional high-quality and high-resolution analog front ends are required to capture non-stationary EEG signals at microvolt levels. The primary components of the proposed setup are the wireless power transmission unit, which consists of a power amplifier, highly efficient resonant-inductive link, rectification, regulation, and power management units, as well as the analog front end, which consists of an analog to digital converter, pre-amplification unit, filtering unit, host microprocessor, and the wireless communication unit. These must all be compatible with the rest of the system and must use the least amount of power possible while minimizing the presence of noise and the attenuation of the recorded signal A highly efficient resonant-inductive coupling link is developed to decrease power transmission dissipation. Magnetized materials were utilized to steer electromagnetic flux and decrease route and medium loss while transmitting the required energy with low dissipation. Signal pre-amplification is handled by the front-end active electrodes. Standard bio-amplifier design approaches are combined to accomplish this purpose, and a thorough investigation of the optimum ADC, microcontroller, and transceiver units has been carried out. We can minimize overall system weight and power consumption by employing battery-less and cable-free EEG readout system designs, consequently giving patients more comfort and freedom of movement. Similarly, the solutions are designed to match the performance of medical-grade equipment. The captured electrical impulses using the proposed setup can be stored for various uses, including classification, prediction, 3D source localization, and for monitoring and diagnosing different brain disorders. All the proposed designs and supporting mathematical derivations were validated through empirical and software-simulated experiments. Many of the proposed designs, including the 3D head cap, the wireless power transmission unit, and the pre-amplification unit, are already fabricated, and the schematic circuits and simulation results were based on Spice, Altium, and high-frequency structure simulator (HFSS) software. The fully integrated head cap to be fabricated would require embedding the active electrodes into the 3D headset and applying current technological advances to miniaturize some of the design elements developed in this dissertation

Nonlinear models and algorithms for RF systems digital calibration

Focusing on the receiving side of a communication system, the current trend in pushing the digital domain ever more closer to the antenna sets heavy constraints on the accuracy and linearity of the analog front-end and the conversion devices. Moreover, mixed-signal implementations of Systems-on-Chip using nanoscale CMOS processes result in an overall poorer analog performance and a reduced yield. To cope with the impairments of the low performance analog section in this "dirty RF" scenario, two solutions exist: designing more complex analog processing architectures or to identify the errors and correct them in the digital domain using DSP algorithms. In the latter, constraints in the analog circuits' precision can be offloaded to a digital signal processor. This thesis aims at the development of a methodology for the analysis, the modeling and the compensation of the analog impairments arising in different stages of a receiving chain using digital calibration techniques. Both single and multiple channel architectures are addressed exploiting the capability of the calibration algorithm to homogenize all the channels' responses of a multi-channel system in addition to the compensation of nonlinearities in each response. The systems targeted for the application of digital post compensation are a pipeline ADC, a digital-IF sub-sampling receiver and a 4-channel TI-ADC. The research focuses on post distortion methods using nonlinear dynamic models to approximate the post-inverse of the nonlinear system and to correct the distortions arising from static and dynamic errors. Volterra model is used due to its general approximation capabilities for the compensation of nonlinear systems with memory. Digital calibration is applied to a Sample and Hold and to a pipeline ADC simulated in the 45nm process, demonstrating high linearity improvement even with incomplete settling errors enabling the use of faster clock speeds. An extended model based on the baseband Volterra series is proposed and applied to the compensation of a digital-IF sub-sampling receiver. This architecture envisages frequency selectivity carried out at IF by an active band-pass CMOS filter causing in-band and out-of-band nonlinear distortions. The improved performance of the proposed model is demonstrated with circuital simulations of a 10th-order band pass filter, realized using a five-stage Gm-C Biquad cascade, and validated using out-of-sample sinusoidal and QAM signals. The same technique is extended to an array receiver with mismatched channels' responses showing that digital calibration can compensate the loss of directivity and enhance the overall system SFDR. An iterative backward pruning is applied to the Volterra models showing that complexity can be reduced without impacting linearity, obtaining state-of-the-art accuracy/complexity performance. Calibration of Time-Interleaved ADCs, widely used in RF-to-digital wideband receivers, is carried out developing ad hoc models because the steep discontinuities generated by the imperfect canceling of aliasing would require a huge number of terms in a polynomial approximation. A closed-form solution is derived for a 4-channel TI-ADC affected by gain errors and timing skews solving the perfect reconstruction equations. A background calibration technique is presented based on cyclo-stationary filter banks architecture. Convergence speed and accuracy of the recursive algorithm are discussed and complexity reduction techniques are applied

Data Acquisition Applications

Data acquisition systems have numerous applications. This book has a total of 13 chapters and is divided into three sections: Industrial applications, Medical applications and Scientific experiments. The chapters are written by experts from around the world, while the targeted audience for this book includes professionals who are designers or researchers in the field of data acquisition systems. Faculty members and graduate students could also benefit from the book

An analogue approach for the processing of biomedical signals

Constant device scaling has signifcantly boosted electronic systems design in the digital domain enabling incorporation of more functionality within small silicon area and at the same time allows high-speed computation. This trend has been exploited for developing high-performance miniaturised systems in a number of application areas like communication, sensor network, main frame computers, biomedical information processing etc. Although successful, the associated cost comes in the form of high leakage power dissipation and systems reliability. With the increase of customer demands for smarter and faster technologies and with the advent of pervasive information processing, these issues may prove to be limiting factors for application of traditional digital design techniques. Furthermore, as the limit of device scaling is nearing, performance enhancement for the conventional digital system design methodology cannot be achieved any further unless innovations in new materials and new transistor design are made. To this end, an alternative design methodology that may enable performance enhancement without depending on device scaling is much sought today.Analogue design technique is one of these alternative techniques that have recently gained considerable interests. Although it is well understood that there are several roadblocks still to be overcome for making analogue-based system design for information processing as the main-stream design technique (e.g., lack of automated design tool, noise performance, efficient passive components implementation on silicon etc.), it may offer a faster way of realising a system with very few components and therefore may have a positive implication on systems performance enhancement. The main aim of this thesis is to explore possible ways of information processing using analogue design techniques in particular in the field of biomedical systems

Design and development of an airborne microwave radiometer for atmospheric sensing

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 103-105).Satellite-based passive microwave remote sensing is a valuable tool for global weather monitoring and prediction. This thesis presents the design and development of a low-cost airborne weather sensing instrument to independently validate a satellite-based sensor platform. The NPOESS Aircraft Sounder Testbed - K-band (NAST-K) is a passive microwave radiometer operating over approximately 200 MHz bandwidth centered at 23.8 GHz and 31.4 GHz, whose data can be used to find surface water, humidity, and temperature conditions. NAST-K flies along with the existing NAST-M instrument at an altitude of 18 km in the NASA ER-2 high altitude aircraft. The primary function of NASTK is to provide coverage of channels 1 and 2 of the Advanced Technology Microwave Sounder (ATMS) aboard the NPOESS Preparatory Project (NPP) satellite, scheduled to be launched in October 2011. The combined NAST-M/K system can validate the performance of ATMS on all channels with data products up to 17km, by underflying the satellite along the same ground track and collecting correlated data. NAST-K has fullwidth at half maximum beamwidths of 7.4° and 6.8° for the two channels respectively, which is approximately consistent with NAST-M. The effective spot size of NAST-K is 2.3km in diameter for the wider 23.8GHz channel at nadir, providing an areal resolution approximately 1000 times greater than ATMS. The major contributions of this thesis include the system-level design of NAST-K, the development of the video amplifier and embedded environmental monitor, and the analysis of the antenna system.by Michael P. Scarito.M.Eng