Deferred setting of scheduling attributes in Ada 2012

© Sáez Barona, S.; Crespo, A. | ACM, 2015. This is the author's version of the work. It is posted here for your personal use. Not for redistribution. The definitive Version of Record was published in Adda Letters, http://dx.doi.org/10.1145/2492312.2492322[EN] Some scheduling techniques, specially in multiprocessor systems, require changing several task attributes atomically to avoid scheduling errors and artifacts. This work proposes to incorporate the deferred attribute setting mechanism to cope with this problem in the next Ada 2012.This work was partially supported by the Vicerectorado de Investigacion of the Universidad Polit ´ ecnica de Valencia under grant PAID-06-10-2397 and European Project OVERSEE (ICT-2009 248333)Sáez Barona, S.; Crespo, A. (2013). Deferred setting of scheduling attributes in Ada 2012. Ada Letters. 33(1):93-100. https://doi.org/10.1145/2492312.2492322S9310033

Session summary: Language abstractions

© Real Sáez, J.| ACM, 2015. This is the author's version of the work. It is posted here for your personal use. Not for redistribution. The definitive Version of Record was published in Adda Letters, http://dx.doi.org/10.1145/2870544.2870558Summary of discussion and conclusions of the IRTAW group around language abstractions.Wellings, A.; Real Sáez, JV. (2015). Session summary: Language abstractions. Ada Letters. 35(1):102-104. doi:10.1145/2870544.2870558S102104351P. Bernardi. Incorporating Cyclic Task Behaviour into Ada Tasks. Ada Letters, This issue, 2015.J. Real and A. Crespo. Incorporating Operating Modes to an Ada Real-Time Framework. Ada Letters, 30(1):73--85, April 2010.S. Sáez, J. Real, and A. Crespo. Implementation of Timing-Event Afinities in Ada/Linux. Ada Letters, This issue, 2015.S. Sáez, S. Terrasa, and A. Crespo. A Real-Time Framework for Multiprocessor Platforms Using Ada 2012. In S. Romanovsky and T. Vardanega, editors, 16th International Conference on Reliable Software technologies -- Ada-Europe 2011, volume 6652. Springer, June 2011.A. Wellings and A. Burns. Interrupts, Timing Events and Dispatching Domains. Ada Letters, This issue, 2015.A. J. Wellings and A. Burns. A Framework for Real-Time Utilities for Ada 2005. Ada Letters, XXVII(2), August 2007

Adding multiprocessor and mode change support to the Ada real-time framework

© ACM, 2013. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in Ada Letters, April 2013, Volume XXXIII, Number 1. http://doi.acm.org/10.1145/2492312.2492324[EN] Based on a previous proposal of an Ada 2005 framework of real-time utilities, this paper deals with the extension of that framework to include support for multiprocessor platforms and multiple operating modes and mode changes. The design of the proposed framework is also intended to be amenable to automatic code generation.This work is partly funded by the Vicerrectorado de Investigacion of Universitat Politècnica de València under grant PAID-06-10-2397 and the Europan Commission’s OVERSEE project (FP7-ICT-2009-4, Project ID 248333).Sáez Barona, S.; Real Sáez, JV.; Crespo Lorente, A. (2013). Adding multiprocessor and mode change support to the Ada real-time framework. Ada Letters. 33(1):116-127. https://doi.org/10.1145/2492312.2492324S11612733

An Integrated Framework for Multiprocessor, Multimoded Real-Time Applications

The final publication is available at Springer via http://dx.doi.org/10.1007/978-3-642-30598-6_2In this paper we propose an approach for building real-time systems under a combination of requirements: specification and handling of operating modes and mode changes; implementation on top of a multiprocessor platform; integration of both aspects within a common framework; and connection with schedulability analysis procedures. The proposed approach uses finite state machines to describe operating modes and transitions, and a framework of real-time utilities that implements the required behaviour in Ada 2012. Automatic code generation plays an important role: the system is derived from the functional and timing specification, and implemented according to the abstractions provided by the framework. Response time analysis enables assessing the schedulability of the different operating modes and the transitions between modes.This work was partially supported by the Vicerrectorado de Investigación of the UPV (PAID-06-10-2397), Ministerio de Ciencia e Innovación (TIN2011-28567-C03- 03) and European Union (FP7-ICT-287702)Sáez Barona, S.; Real Sáez, JV.; Crespo, A. (2012). An Integrated Framework for Multiprocessor, Multimoded Real-Time Applications. En Reliable Software Technologies – Ada-Europe 2012. Springer. 18-34. https://doi.org/10.1007/978-3-642-30598-6_21834Wellings, A.J., Burns, A.: A Framework for Real-Time Utilities for Ada 2005. Ada Letters XXVII(2) (August 2007)Real, J., Crespo, A.: Incorporating Operating Modes to an Ada Real-Time Framework. Ada Letters 30(1) (April 2010)Sáez, S., Terrasa, S., Crespo, A.: A Real-Time Framework for Multiprocessor Platforms Using Ada 2012. In: Romanovsky, A., Vardanega, T. (eds.) Ada-Europe 2011. LNCS, vol. 6652, pp. 46–60. Springer, Heidelberg (2011)Joseph, M., Pandya, P.: Finding response times in a real-time system. British Computer Society Computer Journal 29(5), 390–395 (1986)Audsley, N., Burns, A., Richardson, M., Tindell, K., Wellings, A.J.: Applying new scheduling theory to static priority pre-emptive scheduling. Software Engineering Journal 8(5), 284–292 (1993)Real, J., Crespo, A.: Mode Change Protocols for Real-Time Systems: A Survey and a new Proposal. Real-Time Systems 26(2), 161–197 (2004)Harel, D.: Statecharts: A visual formalism for complex systems. The Science of Computer Programming 8(3), 231–274 (1987)Object Management Group: Unified Modeling Language (OMG UML) V2.4 (August 2011), http://www.omg.org/spec/UML/2.4.1Sáez, S., Terrasa, S., Lorente, V., Crespo, A.: Implementing Reactive Systems with UML State Machines and Ada 2005. In: Kordon, F., Kermarrec, Y. (eds.) Ada-Europe 2009. LNCS, vol. 5570, pp. 149–163. Springer, Heidelberg (2009)Burns, A., Wellings, A.J.: Dispatching Domains for Multiprocessor Platforms and their Representation in Ada. In: Real, J., Vardanega, T. (eds.) Ada-Europe 2010. LNCS, vol. 6106, pp. 41–53. Springer, Heidelberg (2010)Barnett, J.: State Chart XML (SCXML): State Machine Notation for Control Abstraction (May 2008), http://www.w3.org/TR/scxml

A parallel programming model for ada

Over the last three decades, computer architects have been able to achieve an increase in performance for single processors by, e.g., increasing clock speed, introducing cache memories and using instruction level parallelism. However, because of power consumption and heat dissipation constraints, this trend is going to cease. In recent times, hardware engineers have instead moved to new chip architectures with multiple processor cores on a single chip. With multi-core processors, applications can complete more total work than with one core alone. To take advantage of multi-core processors, parallel programming models are proposed as promising solutions for more effectively using multi-core processors. This paper discusses some of the existent models and frameworks for parallel programming, leading to outline a draft parallel programming model for Ada

Operating System Contribution to Composable Timing Behaviour in High-Integrity Real-Time Systems

The development of High-Integrity Real-Time Systems has a high footprint in terms of human, material and schedule costs. Factoring functional, reusable logic in the application favors incremental development and contains costs. Yet, achieving incrementality in the timing behavior is a much harder problem. Complex features at all levels of the execution stack, aimed to boost average-case performance, exhibit timing behavior highly dependent on execution history, which wrecks time composability and incrementaility with it. Our goal here is to restitute time composability to the execution stack, working bottom up across it. We first characterize time composability without making assumptions on the system architecture or the software deployment to it. Later, we focus on the role played by the real-time operating system in our pursuit. Initially we consider single-core processors and, becoming less permissive on the admissible hardware features, we devise solutions that restore a convincing degree of time composability. To show what can be done for real, we developed TiCOS, an ARINC-compliant kernel, and re-designed ORK+, a kernel for Ada Ravenscar runtimes. In that work, we added support for limited-preemption to ORK+, an absolute premiere in the landscape of real-word kernels. Our implementation allows resource sharing to co-exist with limited-preemptive scheduling, which extends state of the art. We then turn our attention to multicore architectures, first considering partitioned systems, for which we achieve results close to those obtained for single-core processors. Subsequently, we shy away from the over-provision of those systems and consider less restrictive uses of homogeneous multiprocessors, where the scheduling algorithm is key to high schedulable utilization. To that end we single out RUN, a promising baseline, and extend it to SPRINT, which supports sporadic task sets, hence matches real-world industrial needs better. To corroborate our results we present findings from real-world case studies from avionic industry

Real-time scheduling in multicore : time- and space-partitioned architectures

Tese de doutoramento, Informática (Engenharia Informática), Universidade de Lisboa, Faculdade de Ciências, 2014The evolution of computing systems to address size, weight and power consumption (SWaP) has led to the trend of integrating functions (otherwise provided by separate systems) as subsystems of a single system. To cope with the added complexity of developing and validating such a system, these functions are maintained and analyzed as components with clear boundaries and interfaces. In the case of real-time systems, the adopted component-based approach should maintain the timeliness properties of the function inside each individual component, regardless of the remaining components. One approach to this issue is time and space partitioning (TSP)—enforcing strict separation between components in the time and space domains. This allows heterogeneous components (different real-time requirements, criticality, developed by different teams and/or with different technologies) to safely coexist. The concepts of TSP have been adopted in the civil aviation, aerospace, and (to some extent) automotive industries. These industries are also embracing multiprocessor (or multicore) platforms, either with identical or nonidentical processors, but are not taking full advantage thereof because of a lack of support in terms of verification and certification. Furthermore, due to the use of the TSP in those domains, compatibility between TSP and multiprocessor is highly desired. This is not the present case, as the reference TSP-related specifications in the aforementioned industries show limited support to multiprocessor. In this dissertation, we defend that the active exploitation of multiple (possibly non-identical) processor cores can augment the processing capacity of the time- and space-partitioned (TSP) systems, while maintaining a compromise with size, weight and power consumption (SWaP), and open room for supporting self-adaptive behavior. To allow applying our results to a more general class of systems, we analyze TSP systems as a special case of hierarchical scheduling and adopt a compositional analysis methodology.Fundação para a Ciência e a Tecnologia (FCT, SFRH/BD/60193/2009, programa PESSOA, projeto SAPIENT); the European Space Agency Innovation (ESA) Triangle Initiative program through ESTEC Contract 21217/07/NL/CB, Project AIR-II; the European Commission Seventh Framework Programme (FP7) through project KARYON (IST-FP7-STREP-288195)

Real-Time Operating Systems and Programming Languages for Embedded Systems

In this chapter, we present the different alternatives that are available today for the development of real-time embedded systems. In particular, we will focus on the programming languages use like C++, Java and Ada and the operating systems like Linux-RT, FreeRTOS, TinyOS, etc. In particular we will analyze the actual state of the art for developing embedded systems under the WORA paradigm with standard Java [1], its Real-Time Specification and with the use of Real-Time Core Extensions and pico Java based CPUs [5]. We expect the reader to have a clear view of the opportunities present at the moment of starting a design with its pros and cons so it can choose the best one to fit its case.Fil: Orozco, Javier Dario. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; Argentina. Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Laboratorio de Sistemas Digitales; ArgentinaFil: Santos, Rodrigo Martin. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; Argentina. Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Laboratorio de Sistemas Digitales; Argentin