SoC Software Components Diagnosis Technology

A novel approach to evaluation of hardware and software testability, represented in the form of register transfer graph, is proposed. Instances of making of software graph models for their subsequent testing and diagnosis are shown.Comment: 4 page

EMULATION TOOL FOR TESTING FAULT TOLERANCE

The aim of this paper is to show a possible adaptation of the well known microprocessor emulation method for testing fault tolerance, and to examine the advantages of the adap-tation. First a survey on test methods and their application will be given with respect to the possibilities for testing fault tolerant architectures. It will be followed by a short overview of different microprocessor fault models, and the fault injection routines based on the fault models. The injection routines require some hardware extension of the con-ventional microprocessor in-circuit emulator. The necessary extensions are shown on a MC68000 based in-circuit emulator. Finally, some improvement possibilities are discussed

Fault-tolerant computer study

A set of building block circuits is described which can be used with commercially available microprocessors and memories to implement fault tolerant distributed computer systems. Each building block circuit is intended for VLSI implementation as a single chip. Several building blocks and associated processor and memory chips form a self checking computer module with self contained input output and interfaces to redundant communications buses. Fault tolerance is achieved by connecting self checking computer modules into a redundant network in which backup buses and computer modules are provided to circumvent failures. The requirements and design methodology which led to the definition of the building block circuits are discussed