Fast algorithm for the 3-D DCT-II

Recently, many applications for three-dimensional (3-D) image and video compression have been proposed using 3-D discrete cosine transforms (3-D DCTs). Among different types of DCTs, the type-II DCT (DCT-II) is the most used. In order to use the 3-D DCTs in practical applications, fast 3-D algorithms are essential. Therefore, in this paper, the 3-D vector-radix decimation-in-frequency (3-D VR DIF) algorithm that calculates the 3-D DCT-II directly is introduced. The mathematical analysis and the implementation of the developed algorithm are presented, showing that this algorithm possesses a regular structure, can be implemented in-place for efficient use of memory, and is faster than the conventional row-column-frame (RCF) approach. Furthermore, an application of 3-D video compression-based 3-D DCT-II is implemented using the 3-D new algorithm. This has led to a substantial speed improvement for 3-D DCT-II-based compression systems and proved the validity of the developed algorithm

Signal Flow Graph Approach to Efficient DST I-IV Algorithms

In this paper, fast and efficient discrete sine transformation (DST) algorithms are presented based on the factorization of sparse, scaled orthogonal, rotation, rotation-reflection, and butterfly matrices. These algorithms are completely recursive and solely based on DST I-IV. The presented algorithms have low arithmetic cost compared to the known fast DST algorithms. Furthermore, the language of signal flow graph representation of digital structures is used to describe these efficient and recursive DST algorithms having $(n-1)$ points signal flow graph for DST-I and $n$ points signal flow graphs for DST II-IV

A fast algorithm for the computation of 2-D forward and inverse MDCT

International audienceA fast algorithm for computing the two-dimensional (2-D) forward and inverse modified discrete cosine transform (MDCT and IMDCT) is proposed. The algorithm converts the 2-D MDCT and IMDCT with block size M N into four 2-D discrete cosine transforms (DCTs) with block size ðM=4Þ ðN=4Þ. It is based on an algorithm recently presented by Cho et al. [An optimized algorithm for computing the modified discrete cosine transform and its inverse transform, in: Proceedings of the IEEE TENCON, vol. A, 21–24 November 2004, pp. 626–628] for the efficient calculation of onedimensional MDCT and IMDCT. Comparison of the computational complexity with the traditional row–column method shows that the proposed algorithm reduces significantly the number of arithmetic operations

Algebraic Signal Processing Theory: Cooley-Tukey Type Algorithms for DCTs and DSTs

This paper presents a systematic methodology based on the algebraic theory of signal processing to classify and derive fast algorithms for linear transforms. Instead of manipulating the entries of transform matrices, our approach derives the algorithms by stepwise decomposition of the associated signal models, or polynomial algebras. This decomposition is based on two generic methods or algebraic principles that generalize the well-known Cooley-Tukey FFT and make the algorithms' derivations concise and transparent. Application to the 16 discrete cosine and sine transforms yields a large class of fast algorithms, many of which have not been found before.Comment: 31 pages, more information at http://www.ece.cmu.edu/~smar

Signal Flow Graph Approach to Efficient DST I-IV Algorithms

In this paper, fast and efficient discrete sine transformation (DST) algorithms are presented based on the factorization of sparse, scaled orthogonal, rotation, rotation-reflection, and butterfly matrices. These algorithms are completely recursive and solely based on DST I-IV. The presented algorithms have low arithmetic cost compared to the known fast DST algorithms. Furthermore, the language of signal flow graph representation of digital structures is used to describe these efficient and recursive DST algorithms having (n�1) points signal flow graph for DST-I and n points signal flow graphs for DST II-IV

Ultrasound Image Filtering and Reconstruction Using DCT/IDCT Filter Structure

In this paper, a new recursive structure based on the convolution model of discrete cosine transform (DCT) for designing of a finite impulse response (FIR) digital filter is proposed. In our derivation, we start with the convolution model of DCT-II to use its Z-transform for the proposed filter structure perspective. Moreover, using the same algorithm, a filter base implementation of the inverse DCT (IDCT) for image reconstruction is developed. The computational time experiments of the proposed DCT/IDCT filter(s) demonstrate that the proposed filters achieve faster elapsed CPU time compared to the direct recursive structures and recursive algorithms for the DCT/IDCT with Arbitrary Length. Experimental results on clinical ultrasound images and comparisons with classical Wiener filter, non-local mean (NLM) filter and total variation (TV) algorithms are used to validate the improvements of the proposed approaches in both noise reduction and reconstruction performance for ultrasound images

Bit-level pipelined digit-serial array processors

A new architecture for high performance digit-serial vector inner product (VIP) which can be pipelined to the bit-level is introduced. The design of the digit-serial vector inner product is based on a new systematic design methodology using radix-2n arithmetic. The proposed architecture allows a high level of bit-level pipelining to increase the throughput rate with minimum initial delay and minimum area. This will give designers greater flexibility in finding the best tradeoff between hardware cost and throughput rate. It is shown that sub-digit pipelined digit-serial structure can achieve a higher throughput rate with much less area consumption than an equivalent bit-parallel structure. A twin-pipe architecture to double the throughput rate of digit-serial multipliers and consequently that of the digit-serial vector inner product is also presented. The effect of the number of pipelining levels and the twin-pipe architecture on the throughput rate and hardware cost are discussed. A two's complement digit-serial architecture which can operate on both negative and positive numbers is also presented