5,167 research outputs found
Automating the IEEE std. 1500 compliance verification for embedded cores
The IEEE 1500 standard for embedded core testing proposes a very effective solution for testing modern system-on-chip (SoC). It proposes a flexible hardware test wrapper architecture, together with a core test language (CTL) used to describe the implemented wrapper functionalities. Already several IP providers have announced compliance in both existing and future design blocks. In this paper we address the challenge of guaranteeing the compliance of a wrapper architecture and its CTL description to the IEEE std. 1500. This is a mandatory step to fully trust the wrapper functionalities in applying the test sequences to the core. The proposed solution aims at implementing a verification framework allowing core providers and/or integrators to automatically verify the compliancy of their products (sold or purchased) to the standar
Desynchronization: Synthesis of asynchronous circuits from synchronous specifications
Asynchronous implementation techniques, which measure logic delays at run time and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst-case delays at design time, and constrain the clock cycle accordingly. De-synchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus permitting widespread adoption of asynchronicity, without requiring special design skills or tools. In this paper, we first of all study different protocols for de-synchronization and formally prove their correctness, using techniques originally developed for distributed deployment of synchronous language specifications. We also provide a taxonomy of existing protocols for asynchronous latch controllers, covering in particular the four-phase handshake protocols devised in the literature for micro-pipelines. We then propose a new controller which exhibits provably maximal concurrency, and analyze the performance of desynchronized circuits with respect to the original synchronous optimized implementation. We finally prove the feasibility and effectiveness of our approach, by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architectur
Are IEEE 1500 compliant cores really compliant to the standard?
Functional verification of complex SoC designs is a challenging task, which fortunately is increasingly supported by automation. This article proposes a verification component for IEEE Std 1500, to be plugged into a commercial verification tool suit
MATLAB as a Design and Verification Tool for the Hardware Prototyping of Wireless Communication Systems
Peer ReviewedPostprint (published version
High-level modelling languages
This paper gives an introduction to the latest developments in modern electronic design methodology. It will give a brief history of the evolution of design software in an attempt to explain the seemingly haphazard development up to the present-day situation
Trojans in Early Design StepsâAn Emerging Threat
Hardware Trojans inserted by malicious foundries
during integrated circuit manufacturing have received substantial
attention in recent years. In this paper, we focus on a different
type of hardware Trojan threats: attacks in the early steps of
design process. We show that third-party intellectual property
cores and CAD tools constitute realistic attack surfaces and that
even system specification can be targeted by adversaries. We
discuss the devastating damage potential of such attacks, the
applicable countermeasures against them and their deficiencies
UVM testbench in Python:feature and performance comparison with SystemVerilog implementation
Abstract. Python is emerging as a new language for functional verification of digital integrated circuits (ICs). With the Python verification framework cocotb enabling to write testbenches in Python, new libraries are being developed for various verification techniques and methodologies, such as functional coverage, constrained random verification and Universal Verification Methodology (UVM). Python testbenches have been used in some research and product development, but there is little information available on their performance, and no studies about applying UVM in Python have been published.
In this thesis, a Python UVM testbench was developed using pyuvm and other Python verification libraries for an AHB-Lite slave IP, and a matching testbench in SystemVerilog was also built to examine the differences in their implementations. Testbench codebase sizes, simulation execution times, memory use and coverage accumulation were compared. The Python testbench had 30% less lines of code, suggesting that testbench development may be faster in Python than SystemVerilog. The execution times of the Python testbench on commercial simulators were 8 to 21 times longer than those of the SystemVerilog testbench in tests with AHB-Lite write operations and random stimulus.
In conclusion, given the performance gap and the UVM Register Abstraction Layer (RAL) being at an early stage of development in pyuvm, the studied Python libraries are not competitive with SystemVerilog and its UVM implementation for verifying complex designs like systems-on-chip (SoCs) at this stage. Nevertheless, pyuvm enables Python programmers and users of open-source simulators without support for SystemVerilog UVM to start using the methodology. A Python UVM testbench based on pyuvm is currently viable for verifying simple designs, and it opens new avenues of research in digital IC verification.TiivistelmÀ. Python on nousemassa uudeksi kieleksi digitaalisten integroitujen piirien varmennukseen. Cocotb-viitekehys mahdollistaa testipenkkien kirjoittamisen Pythonilla, ja uusia Python-kirjastoja kehitetÀÀn eri varmennusmenetelmille, kuten funktionaaliselle kattavuudelle, rajoitetulla satunnaisherÀtteellÀ verifioinnille ja universaalille varmennusmenetelmÀlle (engl. Universal Verification Methodology, UVM). Python-testipenkkejÀ on pienissÀ mÀÀrin kÀytetty tutkimuksissa ja tuotekehityksessÀ, mutta niiden suorituskyvystÀ on hyvin vÀhÀn tietoa, ja UVM:n kÀytöstÀ Pythonilla ei ole julkaistu tutkimuksia.
TĂ€ssĂ€ työssĂ€ kehitettiin UVM-testipenkki Pythonilla AHB-Lite-orjana toimivalle IP-lohkolle kĂ€yttĂ€en pyuvm:ÀÀ ja muita Python-verifiointikirjastoja, ja vastaava testipenkki luotiin myös SystemVerilogilla toteutusten vertailua varten. TestipenkeistĂ€ verrattiin koodikannan kokoa, suoritusaikaa, muistin kĂ€yttöÀ ja kattavuuden kertymistĂ€. Python-testipenkissĂ€ oli 30 % vĂ€hemmĂ€n koodirivejĂ€, mikĂ€ voi merkitĂ€, ettĂ€ testipenkkien kehittĂ€minen Pythonilla on nopeampaa kuin SystemVerilogilla. Suoritusajat kaupallisilla simulaattoreilla oli Python-testipenkillĂ€ 8â21 kertaa pidempiĂ€ kuin SystemVerilog-testipenkillĂ€ testeissĂ€, joissa ajettiin AHB-Lite -kirjoitusoperaatioita ja satunnaisherĂ€tettĂ€.
Koska suorituskykyero oli nÀin merkittÀvÀ, ja koska UVM:n rekisteriabstraktiotaso (engl. Register Abstraction Layer, RAL) on vasta alkutekijöissÀÀn pyuvm:ssÀ, voidaan todeta, ettÀ tutkitut Python-kirjastot eivÀt ole vielÀ nykyisellÀ tasollaan kilpailukykyisiÀ SystemVerilogin ja sen UVM-implementaation kanssa monimutkaisten piirien kuten jÀrjestelmÀpiirien varmennukseen. SiitÀ huolimatta pyuvm mahdollistaa UVM:n kÀytön Python-ohjelmoijille ja avoimen lÀhdekoodin simulaattoreissa, joissa ei ole vielÀ SystemVerilog UVM:lle tukea. Pyuvm-pohjainen Python UVM-testipenkki soveltuu tÀllÀ hetkellÀ yksinkertaisten mallien varmennukseen ja avaa uusia tutkimussuuntia digitaalisten integroitujen piirien varmennukseen
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