Design Techniques for High-Performance SAR A/D Converters

The design of electronics needs to account for the non-ideal characteristics of the device technologies used to realize practical circuits. This is particularly important in mixed analog-digital design since the best device technologies are very different for digital compared to analog circuits. One solution for this problem is to use a calibration correction approach to remove the errors introduced by devices, but this adds complexity and power dissipation, as well as reducing operation speed, and so must be optimised. This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs. ADCs are crucial building blocks in communication systems, in general, and for mobile networks, in particular. The recently launched fifth generation of mobile networks (5G) has required new ADC circuit techniques to meet the higher speed and lower power dissipation requirements for 5G technology. The SAR has become one of the most favoured architectures for designing high-performance ADCs, but the successive nature of the circuit operation makes it difficult to reach ∼GS/s sampling rates at reasonable power consumption. Here, two calibration techniques for high-performance SAR ADCs are presented. The first uses an on-chip stochastic-based mismatch calibration technique that is able to accurately compute and compensate for the mismatch of a capacitive DAC in a SAR ADC. The stochastic nature of the proposed calibration method enables determination of the mismatch of the CAPDAC with a resolution much better than that of the DAC. This allows the unit capacitor to scale down to as low as 280aF for a 9-bit DAC. Since the CAP-DAC causes a large part of the overall dynamic power consumption and directly determines both the sizes of the driving and sampling switches and the size of the input capacitive load of the ADC and the kT/C noise power, a small CAP-DAC helps the power efficiency. To validate the proposed calibration idea, a 10-bit asynchronous SAR ADC was fabricated in 28-nm CMOS. Measurement results show that the proposed stochastic calibration improves the ADC’s SFDR and SNDR by 14.9 dB, 11.5 dB, respectively. After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s. The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique and the timing-skew calibration technique enables a TI SAR ADC to be designed that can achieve a sampling rate of ∼GS/s with 10-bit resolution and a power consumption as low as ∼10mW; specifications that satisfy the requirements of 5G technology

데이터 전송로 확장성과 루프 선형성을 향상시킨 다중채널 수신기들에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 2. 정덕균.Two types of serial data communication receivers that adopt a multichannel architecture for a high aggregate I/O bandwidth are presented. Two techniques for collaboration and sharing among channels are proposed to enhance the loop-linearity and channel-expandability of multichannel receivers, respectively. The first proposed receiver employs a collaborative timing scheme recovery which relies on the sharing of all outputs of phase detectors (PDs) among channels to extract common information about the timing and multilevel signaling architecture of PAM-4. The shared timing information is processed by a common global loop filter and is used to update the phase of the voltage-controlled oscillator with better rejection of per-channel noise. In addition to collaborative timing recovery, a simple linearization technique for binary PDs is proposed. The technique realizes a high-rate oversampling PD while the hardware cost is equivalent to that of a conventional 2x-oversampling clock and data recovery. The first receiver exploiting the collaborative timing recovery architecture is designed using 45-nm CMOS technology. A single data lane occupies a 0.195-mm2 area and consumes a relatively low 17.9 mW at 6 Gb/s at 1.0V. Therefore, the power efficiency is 2.98 mW/Gb/s. The simulated jitter is about 0.034 UI RMS given an input jitter value of 0.03 UI RMS, while the relatively constant loop bandwidth with the PD linearization technique is about 7.3-MHz regardless of the data-stream noise. Unlike the first receiver, the second proposed multichannel receiver was designed to reduce the hardware complexity of each lane. The receiver employs shared calibration logic among channels and yet achieves superior channel expandability with slim data lanes. A shared global calibration control, which is used in a forwarded clock receiver based on a multiphase delay-locked loop, accomplishes skew calibration, equalizer adaptation, and the phase lock of all channels during a calibration period, resulting in reduced hardware overhead and less area required by each data lane. The second forwarded clock receiver is designed in 90-nm CMOS technology. It achieves error-free eye openings of more than 0.5 UI across 9− 28 inch Nelco 4000-6 microstrips at 4− 7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only 0.152 mm2 and consumes 69.8 mW, while the rest of the receiver occupies 0.297 mm2 and consumes 56 mW at a data rate of 7 Gb/s and a supply voltage of 1.35 V.1. Introduction 1 1.1 Motivations 1.2 Thesis Organization 2. Previous Receivers for Serial-Data Communications 2.1 Classification of the Links 2.2 Clocking architecture of transceivers 2.3 Components of receiver 2.3.1 Channel loss 2.3.2 Equalizer 2.3.3 Clock and data recovery circuit 2.3.3.1. Basic architecture 2.3.3.2. Phase detector 2.3.3.2.1. Linear phase detector 2.3.3.2.2. Binary phase detector 2.3.3.3. Frequency detector 2.3.3.4. Charge pump 2.3.3.5. Voltage controlled oscillator and delay-line 2.3.4 Loop dynamics of PLL 2.3.5 Loop dynamics of DLL 3. The Proposed PLL-Based Receiver with Loop Linearization Technique 3.1 Introduction 3.2 Motivation 3.3 Overview of binary phase detection 3.4 The proposed BBPD linearization technique 3.4.1 Architecture of the proposed PLL-based receiver 3.4.2 Linearization technique of binary phase detection 3.4.3 Rotational pattern of sampling phase offset 3.5 PD gain analysis and optimization 3.6 Loop Dynamics of the 2nd-order CDR 3.7 Verification with the time-accurate behavioral simulation 3.8 Summary 4. The Proposed DLL-Based Receiver with Forwarded-Clock 4.1 Introduction 4.2 Motivation 4.3 Design consideration 4.4 Architecture of the proposed forwarded-clock receiver 4.5 Circuit description 4.5.1 Analog multi-phase DLL 4.5.2 Dual-input interpolating deley cells 4.5.3 Dedicated half-rate data samplers 4.5.4 Cherry-Hooper continuous-time linear equalizer 4.5.5 Equalizer adaptation and phase-lock scheme 4.6 Measurement results 5. Conclusion 6. BibliographyDocto

Techniques for high-performance digital frequency synthesis and phase control

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 183-190).This thesis presents a 3.6-GHz, 500-kHz bandwidth digital [delta][sigma] frequency synthesizer architecture that leverages a recently invented noise-shaping time-to-digital converter (TDC) and an all-digital quantization noise cancellation technique to achieve excellent in-band and out-of-band phase noise, respectively. In addition, a passive digital-to-analog converter (DAC) structure is proposed as an efficient interface between the digital loop filter and a conventional hybrid voltage-controlled oscillator (VCO) to create a digitally-controlled oscillator (DCO). An asynchronous divider structure is presented which lowers the required TDC range and avoids the divide-value-dependent delay variation. The prototype is implemented in a 0.13-am CMOS process and its active area occupies 0.95 mm². Operating under 1.5 V, the core parts, excluding the VCO output buffer, dissipate 26 mA. Measured phase noise at 3.67 GHz achieves -108 dBc/Hz and -150 dBc/Hz at 400 kHz and 20 MHz, respectively. Integrated phase noise at this carrier frequency yields 204 fs of jitter (measured from 1 kHz to 40 MHz). In addition, a 3.2-Gb/s delay-locked loop (DLL) in a 0.18-[mu]m CMOS for chip-tochip communications is presented. By leveraging the fractional-N synthesizer technique, this architecture provides a digitally-controlled delay adjustment with a fine resolution and infinite range. The provided delay resolution is less sensitive to the process, voltage, and temperature variations than conventional techniques. A new [delta][sigma] modulator enables a compact and low-power implementation of this architecture. A simple bang-bang detector is used for phase detection. The prototype operates at a 1.8-V supply voltage with a current consumption of 55 mA. The phase resolution and differential rms clock jitter are 1.4 degrees and 3.6 ps, respectively.by Chun-Ming Hsu.Ph.D

Resilient Peer-to-Peer Ranging using Narrowband High-Performance Software-Defined Radios for Mission-Critical Applications

There has been a growing need for resilient positioning for numerous applications of the military and emergency services that routinely conduct operations that require an uninterrupted positioning service. However, the level of resilience required for these applications is difficult to achieve using the popular navigation and positioning systems available at the time of this writing. Most of these systems are dependent on existing infrastructure to function or have certain vulnerabilities that can be too easily exploited by hostile forces. Mobile ad-hoc networks can bypass some of these prevalent issues making them an auspicious topic for positioning and navigation research and development. Such networks consist of portable devices that collaborate to form wireless communication links with one another and collectively carry out vital network functions independent of any fixed centralized infrastructure. The purpose of the research presented in this thesis is to adapt the protocols of an existing narrowband mobile ad-hoc communications system provided by Terrafix to enable range measuring for positioning. This is done by extracting transmission and reception timestamps of signals exchanged between neighbouring radios in the network with the highest precision possible. However, many aspects of the radios forming this network are generally not conducive to precise ranging, so the ranging protocols implemented need to either maneuver around these shortcomings or compensate for loss of precision caused. In particular, the narrow bandwidth of the signals that drastically reduces the resolution of symbol timing. The objective is to determine what level of accuracy and precision is possible using this radio network and whether one can justify investment for further development. Early experiments have provided a simple ranging demonstration in a benign environment, using the existing synchronization protocols, by extracting time data. The experiments have then advanced to the radio’s signal processing to adjust the synchronization protocols for maximize symbol timing precision and correct for clock drift. By implementing innovative synchronization techniques to the radio network, ranging data collected under benign conditions can exhibit a standard deviation of less than 3m. The lowest standard deviation achieved using only the existing methods of synchronization was over two orders of magnitude greater. All this is achieved in spite of the very narrow 10−20kHz bandwidth of the radio signals, which makes producing range estimates with an error less than 10−100m much more challenging compared to wider bandwidth systems. However, this figure is beholden to the relative motion of neighbouring radios in the network and how frequently range estimates need to be made. This thesis demonstrates how such a precision may be obtained and how this figure is likely to hold up when applied in conditions that are not ideal

Chemotactic Responses of Tethered Bacteria

Escherichia coli swim in a three-dimensional random walk of alternating runs and tumbles, using their flagella for propulsion. When moving in a gradient of an attractant or repellent, they bias the walk in such a way as to migrate into a favorable region; this is a basis for chemotaxis. Bacteria may be tethered to a glass surface by means of a single flagellum. When tethered, cell bodies spin alternately clockwise (CW) and counterclockwise (CCW) under the influence of the rotary motor that drives the flagellum. The CCW state corresponds to the run mode and the CW state to the tumble mode. Tethered bacteria remain fixed in place, thereby providing an opportunity to study chemotactic behavior by direct manipulation of attractant or repellent concentration near the cells. Two experimental approaches have been used to exploit this opportunity. In the first, a mixing device that provides programmable concentration changes was used to stimulate tethered cells with exponential temporal gradients or exponentiated sine waves of the attractant α-methyl-D,L-aspartate. Such changes cause chemoreceptor occupancy to be changed linearly or sinusoidally, respectively. Exponential temporal gradients (both positive and negative) were found to shift the rotational bias (defined as the fraction of time spent spinning CCW) by a fixed amount related to the steepness of the gradient. The bias shifts produced indicate that cells are exquisitely sensitive to small changes in chemoreceptor occupancy. Distributions of CW and CCW intervals remained exponential during such gradients. This result is inconsistent with a response regulator model in which rotational transitions are associated with level-crossings of a fluctuating, hypothetical intermediate. It is consistent with a model in which transitions occur at random between rotational states, the transition probabilities being governed by chemotactic signals. In the second approach, short bursts of an attractant or repellent were delivered iontophoretically, producing an impulse response in the tethered bacteria. Properties of the impulse response show both adaptive and integrative behavior, and imply that cells respond maximally to changes in concentration which occur over times comparable with the length of a run. The impulse response can be used to predict the behavior of cells towards an arbitrary stimulus in the linear domain. Impulse responses from a series of chemotaxis mutants showed that some were defective in adaptation but not excitation; others were defective in both. Taken together, the experiments provide information about the spectral response of bacteria to concentration changes with frequencies ranging from 10-3 Hz up to almost 10 Hz. Both sets of data are consistent with the notion of a cellular "bias regulator" signal that sets the transition probabilities between two states; one representing CCW and the other representing CW rotation.</p

A time-based approach for multi-GHz embedded mixed-signal characterization and measurement /

The increasingly more sophisticated systems that are nowadays implemented on a single chip are placing stringent requirements on the test industry. New test strategies, equipment, and methodologies need to be developed to sustain the constant increase in demand for consumer and communication electronics. Techniques for built-in-self-test (BIST) and design-for-test (DFT) strategies have been proven to offer more feasible and economical testing solutions.Previous works have been conducted to perform on-chip testing, characterization, and measurement of signals and components. The current thesis advances those techniques on many levels. In terms of performance, an increase of more than an order of magnitude in speed is achieved. 70-GHz (effective sampling) on-chip oscilloscope is reported, compared to 4-GHz and 10-GHz ones in previous state-of-the-art implementations. Power dissipation is another area where the proposed work offer a superior solution compared to previous alternatives. All the proposed circuits do not exceed a few milliWatts of power dissipation, while performing multi-GHz high-speed signal capture at a medium resolution. Finally, and possibly most importantly, all the proposed circuits for test rely on a different form of signal processing; the time-based approach. It is believed that this approach paves the path to a lot of new techniques and circuit design skills that can be investigated more deeply. As an integral part of the time-based processing approach for GHz signal capture, this thesis verifies the advantages of using time amplification. The use of such amplification in the time domain is materialized with experimental results from three specific integrated circuits achieving different tasks in GHz high-speed in-situ signal measurement and characterization. Advantages of using such time-based approach techniques, when combined with the use of a front-end time amplifier, include noise immunity, the use of synthesizable digital cells, and circuit building blocks that track the technology scaling in terms of area and speed

Physiology, Psychoacoustics and Cognition in Normal and Impaired Hearing

​The International Symposium on Hearing is a prestigious, triennial gathering where world-class scientists present and discuss the most recent advances in the field of human and animal hearing research. The 2015 edition will particularly focus on integrative approaches linking physiological, psychophysical and cognitive aspects of normal and impaired hearing. Like previous editions, the proceedings will contain about 50 chapters ranging from basic to applied research, and of interest to neuroscientists, psychologists, audiologists, engineers, otolaryngologists, and artificial intelligence researchers.