Variable Bandwidth Analog Channel Filters for Software Defined Radio

An important aspect of Software Defined Radio is the ability to define the bandwidth of the filter that selects the desired channel. This paper first explains the importance of channel filtering. Then the advantage of analog channel filtering with a variable bandwidth in a Software Defined Radio is demonstrated. This is done by comparing the requirements of the analog-to-digital converter with and without an analog filter with a variable bandwidth. Then, a technique for channel filtering is described, in which two passive filters are combined to obtain a variable bandwidth. Passive filters have the advantage of high linearity, low noise and inherent energy efficiency. Some limitations of the concept are discussed. Finally, conclusions are drawn and our ideas for further research are presented

Jitter requirements of the sampling clock in software radio receivers

The effective number of bits of an analog-to-digital converter (ADC) is not only limited by the quantization step inaccuracy but also by sampling time uncertainty. According to a commonly used model, the error caused by timing jitter, integrated over the whole bandwidth, should not be bigger than the quantization noise, for a full swing input signals at the maximum input frequency. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. However, for a radio receiver not the total integrated error is relevant, but only the error signal in the channel bandwidth. This paper explores the clock jitter requirements for a software radio application, using a more realistic model and taking into account the power spectrum of both the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter requirements are very similar to reciprocal mixing requirements of superheterodyne receivers

A flexible GPU-accelerated radio-frequency readout for superconducting detectors

We have developed a flexible radio-frequency readout system suitable for a variety of superconducting detectors commonly used in millimeter and submillimeter astrophysics, including kinetic inductance detectors (KIDs), Thermal KID bolometers, and quantum capacitance detectors. Our system avoids custom FPGA-based readouts and instead uses commercially available software radio hardware for analog to digital converter chip/digital to analog converter chip and a GPU to handle real-time signal processing. Because this system is written in common C++/CUDA, the range of different algorithms that can be quickly implemented make it suitable for the readout of many others cryogenic detectors and for the testing of different and possibly more effective data acquisition schemes

A flexible GPU-accelerated radio-frequency readout for superconducting detectors

We have developed a flexible radio-frequency readout system suitable for a variety of superconducting detectors commonly used in millimeter and submillimeter astrophysics, including kinetic inductance detectors (KIDs), Thermal KID bolometers, and quantum capacitance detectors. Our system avoids custom FPGA-based readouts and instead uses commercially available software radio hardware for analog to digital converter chip/digital to analog converter chip and a GPU to handle real-time signal processing. Because this system is written in common C++/CUDA, the range of different algorithms that can be quickly implemented make it suitable for the readout of many others cryogenic detectors and for the testing of different and possibly more effective data acquisition schemes

A Software Radio Based Ionosonde Using GNU Radio

ABSTRACT The Canadian Advanced Digital Ionosonde (CADI) is used to study and investigate the structure and motion o f the ionosphere. The main components of CADI are implemented in microcontroller based digital logic. Due to the increased speed and reconfiguration capability of modem FPGAs (Field Programmable Gate Arrays) and ADCs (Analog-Digital Converters), this project is aimed to develop an ionosonde based on an open source radio software platform, GNU Radio, in conjunction with its hardware support, the Universal Software Radio Peripheral (USRP). The lowest cost FPGA, Cyclone EP1C12Q240C8 is selected to control Analog Digital Converter to transmit a HF (High Frequency) signal and to decimate and down convert the signal at the receiver side, which is controlled by a USB controller, and to load the FPGA configuration image through GNU radio platform. To obtain a good range resolution and low noise level, the signal is modulated by a 113-bit Legendre sequence with a preamble packed at front for synchronization. Based on the experimental results, the discussion and conclusion are included

Design and Implementation of an RF Front-End for Software Defined Radios

Software Defined Radios have brought a major reformation in the design standards for radios, in which a large portion of the functionality is implemented through pro­ grammable signal processing devices, giving the radio the ability to change its op­ erating parameters to accommodate new features and capabilities. A software radio approach reduces the content of radio frequency and other analog components of the traditional radios and emphasizes digital signal processing to enhance overall receiver flexibility. Field Programmable Gate Arrays (FPGA) are a suitable technology for the hardware platform as they offer the potential of hardware-like performance coupled with software-like programmability. Software defined radio is a very broad field, encompassing the design of various technologies all the way from the antenna to RF, IF, and baseband digital design. The RF section primarily consists of analog hardware modules. The IF and baseband sections are primarily digital. It is the general process of the radio to convert the incoming signal from RF to IF and then IF to baseband for better signal processing system. In this thesis, some of major building blocks of a Software defined radio are de­ signed and implemented using FPGAs. The design of a Digital front end, which provides the bridge between the baseband and analog RF portions of a wireless receiver, is synthesized. The Digital front end receiver consists of a digital down converter(DDC) which in turn comprises of a direct digital frequency synthesizer (DDFS), a phase accumulator and a low pass filter. The signal processing block of the DDFS is executed using Co-ordinate Rotation Digital Computer (CORDIC) iii Abstract algorithm. Cascaded-Integrator-Comb filters (CIC) are implemented for changing the sample rate of the incoming data. Application of a DDC includes software ra­ dios, multicarrier, multimode digital receivers, micro and pico cell systems,broadband data applications, instrumentation and test equipment and in-building wireless tele­ phony. Also, in this thesis, interfaces for connecting Texas Instruments high speed and high resolution Analog-to-Digital converters (ADC) and Digital-to-Analog converters (DAC) with Xilinx Virtex-5 FPGAs are also implemented and demonstrated

Direct Digital Frequency Synthesizer Architecture for Wireless Communication in 90 NM CMOS Technology

Software radio is one promising field that can meet the demands for low cost, low power, and high speed electronic devices for wireless communication. At the heart of software radio is a programmable oscillator called a Direct Digital Synthesizer (DDS). DDS has the capabilities of rapid frequency hopping by digital software control while operating at very high frequencies and having sub-hertz resolution. Nevertheless, the digital-to-analog converter (DAC) and the read-only-memory (ROM) look-up table, building blocks of the DDS, prevent the DDS to be used in wireless communication because they introduce errors and noises to the DDS and their performances deteriorate at high speed. The DAC and ROM are replaced in this thesis by analog active filters that convert the square wave output of the phase accumulator directly into a sine wave. The proposed architecture operates with a reference clock of 9.09 GHz and can be fully-integrated in 90 nm CMOS technology

A Wideband Inductorless CMOS Front-End for Software Defined

The number of wireless communication links is witnessing tremendous growth and new standards are being introduced at high pace. These standards heavily rely on digital signal processing, making CMOS the first technology of choice. However, RF CMOS circuit development is costly and time consuming due to mask costs and design iterations. This pleads for a Software Defined Radio approach, in which one piece of flexible radio hardware is re-used for different applications and standards, downloadable and under software control. To the best of our knowledge, little work has been done in this field based on CMOS technology. Recently, a bipolar downconverter front-end has been proposed [1]. In CMOS, only wideband low-noise amplifiers have been proposed, and some CMOS tuner ICs for satellite reception (which have less stringent noise requirements because they are preceded by an outdoor low-noise converter). This paper presents a wideband RF downconverter frontend in 0.18 um CMOS (also published in [2]), designed in the context of a research project exploring the feasibility of software defined radio, using a combined Bluetooth/WLAN receiver as a vehicle. Usually, RF receivers are optimised for low power consumption. In contrast, we have taken the approach to optimise for flexibility. The paper discusses the main system and circuit design choices, and assesses the achievable performance via measurements on a front-end implemented in 0.18um CMOS. The flexible design achieves a 0.2-2.2 GHz -3 dB bandwidth, a gain of 25 dB with 6 dB noise figure and +1 dBm IIP3

Implementación y configuración de un receptor de radio definido por software (SDR) para estudios de propagación

The constant development of digital systems in radio communications demands the adaptation of the current receiving equipment to the new technologies. In this context, a new Software Defined Radio based receiver is being implemented with the aim of carrying out different experiments to analyze the propagation of signals through the atmosphere from a satellite beacon. The receiver selected for this task is the PERSEUS SDR from the Italian company Microtelecom s.r.l. It is a software defined VLF-LF-MF-HF receiver based on an outstanding direct sampling digital architecture which features a 14 bit 80 MSamples/s analog-to-digital converter, a high-performance FPGA-based digital down-converter and a high-speed 480 Mbit/s USB2.0 PC interface. The main goal is to implement the related software and adapt the new receiver to the current working environment. In this paper, SDR technology guidelines are given and PERSEUS receiver digital signal processing is presented with the most remarkable results

An Innovative Technique for Water Leak Detection Stemming from Radio Astronomy : A Potential University Technology Transfer

There have been many documented cases of technology transfer from astronomy to other disciplines such as medicine, for example, a system for diagnosing breast cancer utilising software originally developed to mosaic planetary images. The approach taken in this research will involve using a technology originally developed for radio astronomy to detect water leaks in pipes that are part of water networks in various infrastructure systems. This is innovative research as it involves an interdisciplinary approach to explore a technology and evaluate its commercial potential. Experiments are underway in which signals from an acoustic phased array are amplified and digitized using a multichannel analogue-to-digital (ADC) converter and analysed using a software correlation technique to identify leak signatures. Therefore, the chosen technology’s commercialisibility will be tested for alternate applications which can be applied to infrastructures such as water networks. In addition, the importance of interdisciplinary research will also be reflected through this research