Using discrete-time hyperchaotic-based asymmetric encryption and decryption keys for secure signal transmission

In this paper, a framework for the synchronization of two non-identical discrete-time hyperchaotic systems, namely the 3D Baier-Klein and the 3D Hitzel-Zele maps, based on the use of hybrid output feedback concept and aggregation techniques, is employed to design a two-channel secure communication system. New sufficient conditions for synchronization are obtained by the use of Borne and Gentina practical criterion for stabilization study associated to the forced arrow form matrix for system description. The efficiency of the proposed approach to confidentially recover the transmitted message signal is shown via an application to the hyperchaotic Baier-Klein and Hitzel-Zele systems, considered as generators of asymmetric encryption and decryption keys

Design of Discrete-time Chaos-Based Systems for Hardware Security Applications

Security of systems has become a major concern with the advent of technology. Researchers are proposing new security solutions every day in order to meet the area, power and performance specifications of the systems. The additional circuit required for security purposes can consume significant area and power. This work proposes a solution which utilizes discrete-time chaos-based logic gates to build a system which addresses multiple hardware security issues. The nonlinear dynamics of chaotic maps is leveraged to build a system that mitigates IC counterfeiting, IP piracy, overbuilding, disables hardware Trojan insertion and enables authentication of connecting devices (such as IoT and mobile). Chaos-based systems are also used to generate pseudo-random numbers for cryptographic applications.The chaotic map is the building block for the design of discrete-time chaos-based oscillator. The analog output of the oscillator is converted to digital value using a comparator in order to build logic gates. The logic gate is reconfigurable since different parameters in the circuit topology can be altered to implement multiple Boolean functions using the same system. The tuning parameters are control input, bifurcation parameter, iteration number and threshold voltage of the comparator. The proposed system is a hybrid between standard CMOS logic gates and reconfigurable chaos-based logic gates where original gates are replaced by chaos-based gates. The system works in two modes: logic locking and authentication. In logic locking mode, the goal is to ensure that the system achieves logic obfuscation in order to mitigate IC counterfeiting. The secret key for logic locking is made up of the tuning parameters of the chaotic oscillator. Each gate has 10-bit key which ensures that the key space is large which exponentially increases the computational complexity of any attack. In authentication mode, the aim of the system is to provide authentication of devices so that adversaries cannot connect to devices to learn confidential information. Chaos-based computing system is susceptible to process variation which can be leveraged to build a chaos-based PUF. The proposed system demonstrates near ideal PUF characteristics which means systems with large number of primary outputs can be used for authenticating devices

Pseudo-Random Bit Generator Using Chaotic Seed for Cryptographic Algorithm in Data Protection of Electric Power Consumption

Cryptographic algorithms have played an important role in information security for protecting privacy. The literature provides evidence that many types of chaotic cryptosystems have been proposed. These chaotic systems encode information to obviate its orbital instability and ergodicity. In this work, a pseudo-random cryptographic generator algorithm with a symmetric key, based on chaotic functions, is proposed. Moreover, the algorithm exploits dynamic simplicity and synchronization to generate encryption sub-keys using unpredictable seeds, extracted from a chaotic zone, in order to increase their level of randomness. Also, it is applied to a simulated electrical energy consumption signal and implemented on a prototype, using low hardware resources, to measure physical variables; hence, the unpredictability degree was statistically analyzed using the resulting cryptogram. It is shown that the pseudo-random sequences produced by the cryptographic key generator have acceptable properties with respect to randomness, which are validated in this paper using National Institute of Standards and Technology (NIST) statistical tests. To complement the evaluation of the encrypted data, the Lena image is coded and its metrics are compared with those reported in the literature, yielding some useful results

Chaotic multi-objective optimization based design of fractional order PI{\lambda}D{\mu} controller in AVR system

In this paper, a fractional order (FO) PI{\lambda}D\mu controller is designed to take care of various contradictory objective functions for an Automatic Voltage Regulator (AVR) system. An improved evolutionary Non-dominated Sorting Genetic Algorithm II (NSGA II), which is augmented with a chaotic map for greater effectiveness, is used for the multi-objective optimization problem. The Pareto fronts showing the trade-off between different design criteria are obtained for the PI{\lambda}D\mu and PID controller. A comparative analysis is done with respect to the standard PID controller to demonstrate the merits and demerits of the fractional order PI{\lambda}D\mu controller.Comment: 30 pages, 14 figure

Self-balanced real-time photonic scheme for ultrafast random number generation

We propose a real-time self-balanced photonic method for extracting ultrafast random numbers from broadband randomness sources. In place of electronic analog-to-digital converters (ADCs), the balanced photo-detection technology is used to directly quantize optically sampled chaotic pulses into a continuous random number stream. Benefitting from ultrafast photo-detection, our method can efficiently eliminate the generation rate bottleneck from electronic ADCs which are required in nearly all the available fast physical random number generators. A proof-of-principle experiment demonstrates that using our approach 10 Gb/s real-time and statistically unbiased random numbers are successfully extracted from a bandwidth-enhanced chaotic source. The generation rate achieved experimentally here is being limited by the bandwidth of the chaotic source. The method described has the potential to attain a real-time rate of 100 Gb/s

A Novel TRNG Based on Traditional ADC Nonlinear Effect and Chaotic Map for IoT Security and Anticollision

In the rapidly developing Internet of Things (IoT) applications, how to achieve rapid identification of massive devices and secure the communication of wireless data based on low cost and low power consumption is the key problem to be solved urgently. This paper proposes a novel true random number generator (TRNG) based on ADC nonlinear effect and chaotic map, which can be implemented by traditional processors with built-in ADCs, such as MCU, DSP, ARM, and FPGA. The processor controls the ADC to sample the changing input signal to obtain the digital signal DADC and then extracts some bits of DADC to generate the true random number (TRN). At the same time, after a delay based on DADC, the next time ADC sampling is carried out, and the cycle continues until the processor stops generating the TRN. Due to the nonlinear effect of ADC, the DADC obtained from each sampling is stochastic, and the changing input signal will sharply change the delay time, thus changing the sampling interval (called random interval sampling). As the input signal changes, DADC with strong randomness is obtained. The whole operation of the TRNG resembles a chaotic map, and this method also eliminates the pseudorandom property of chaotic map by combining the variable input signal (including noise) with the nonlinear effect of ADC. The simulation and actual test data are verified by NIST, and the verification results show that the random numbers generated by the proposed method have strong randomness and can be used to implement TRNG. The proposed TRNG has the advantages of low cost, low power consumption, and strong compatibility, and the rate of generating true random number is more than 1.6 Mbps (determined by ADC sampling rate and processor frequency), which is very suitable for IoT sensor devices for security encryption algorithms and anticollision

CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current