Analysis of Internally Bandlimited Multistage Cubic-Term Generators for RF Receivers

Adaptive feedforward error cancellation applied to correct distortion arising from third-order nonlinearities in RF receivers requires low-noise low-power reference cubic nonidealities. Multistage cubic-term generators utilizing cascaded nonlinear operations are ideal in this regard, but the frequency response of the interstage circuitry can introduce errors into the cubing operation. In this paper, an overview of the use of cubic-term generators in receivers relative to other applications is presented. An interstage frequency response plan is presented for a receiver cubic-term generator and is shown to function for arbitrary three-signal third-order intermodulation generation. The noise of such circuits is also considered and is shown to depend on the total incoming signal power across a particular frequency band. Finally, the effects of the interstage group delay are quantified in the context of a relevant communication standard requirement

Linearization techniques to suppress optical nonlinearity

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.This thesis is shown the implementation of the linearization techniques such as feedforward and pre-distortion feedback linearization to suppress the optical components nonlinearities caused by the fibre and semiconductor optical amplifier (SOA). The simulation verified these two linearization techniques for single tone direct modulation, two tone indirect modulation and ultra wideband input to the optical fibre. These techniques uses the amplified spontaneously emission (ASE) noise reduction in two loops of SOA by a feed-forward and predistortion linearizer and is shown more than 6dB improvement. Also it investigates linearization for the SOA amplifier to cancel out the third order harmonics or inter-modulation distortion (IMD) or four waves mixing. In this project, more than 20 dB reductions is seen in the spectral re-growth caused by the SOA. Amplifier non-linearity becomes more severe with two strong input channels leading to inter-channel distortion which can completely mask a third adjacent channel. The simulations detailed above were performed utilizing optimum settings for the variable gain, phase and delay components in the error correction loop of the feed forward and Predistortion systems and hence represent the ideal situation of a perfect feed-forward and Predistortion system. Therefore it should be consider that complexity of circuit will increase due to amplitude, phase and delay mismatches in practical design. Also it has describe the compatibility of Software Defined Radio with Hybrid Fibre Radio with simulation model of wired optical networks to be used for future research investigation, based on the star and ring topologies for different modulation schemes, and providing the performance for these configurations

Dirty RF Signal Processing for Mitigation of Receiver Front-end Non-linearity

Moderne drahtlose Kommunikationssysteme stellen hohe und teilweise gegensätzliche Anforderungen an die Hardware der Funkmodule, wie z.B. niedriger Energieverbrauch, große Bandbreite und hohe Linearität. Die Gewährleistung einer ausreichenden Linearität ist, neben anderen analogen Parametern, eine Herausforderung im praktischen Design der Funkmodule. Der Fokus der Dissertation liegt auf breitbandigen HF-Frontends für Software-konfigurierbare Funkmodule, die seit einigen Jahren kommerziell verfügbar sind. Die praktischen Herausforderungen und Grenzen solcher flexiblen Funkmodule offenbaren sich vor allem im realen Experiment. Eines der Hauptprobleme ist die Sicherstellung einer ausreichenden analogen Performanz über einen weiten Frequenzbereich. Aus einer Vielzahl an analogen Störeffekten behandelt die Arbeit die Analyse und Minderung von Nichtlinearitäten in Empfängern mit direkt-umsetzender Architektur. Im Vordergrund stehen dabei Signalverarbeitungsstrategien zur Minderung nichtlinear verursachter Interferenz - ein Algorithmus, der besser unter "Dirty RF"-Techniken bekannt ist. Ein digitales Verfahren nach der Vorwärtskopplung wird durch intensive Simulationen, Messungen und Implementierung in realer Hardware verifiziert. Um die Lücken zwischen Theorie und praktischer Anwendbarkeit zu schließen und das Verfahren in reale Funkmodule zu integrieren, werden verschiedene Untersuchungen durchgeführt. Hierzu wird ein erweitertes Verhaltensmodell entwickelt, das die Struktur direkt-umsetzender Empfänger am besten nachbildet und damit alle Verzerrungen im HF- und Basisband erfasst. Darüber hinaus wird die Leistungsfähigkeit des Algorithmus unter realen Funkkanal-Bedingungen untersucht. Zusätzlich folgt die Vorstellung einer ressourceneffizienten Echtzeit-Implementierung des Verfahrens auf einem FPGA. Abschließend diskutiert die Arbeit verschiedene Anwendungsfelder, darunter spektrales Sensing, robuster GSM-Empfang und GSM-basiertes Passivradar. Es wird gezeigt, dass nichtlineare Verzerrungen erfolgreich in der digitalen Domäne gemindert werden können, wodurch die Bitfehlerrate gestörter modulierter Signale sinkt und der Anteil nichtlinear verursachter Interferenz minimiert wird. Schließlich kann durch das Verfahren die effektive Linearität des HF-Frontends stark erhöht werden. Damit wird der zuverlässige Betrieb eines einfachen Funkmoduls unter dem Einfluss der Empfängernichtlinearität möglich. Aufgrund des flexiblen Designs ist der Algorithmus für breitbandige Empfänger universal einsetzbar und ist nicht auf Software-konfigurierbare Funkmodule beschränkt.Today's wireless communication systems place high requirements on the radio's hardware that are largely mutually exclusive, such as low power consumption, wide bandwidth, and high linearity. Achieving a sufficient linearity, among other analogue characteristics, is a challenging issue in practical transceiver design. The focus of this thesis is on wideband receiver RF front-ends for software defined radio technology, which became commercially available in the recent years. Practical challenges and limitations are being revealed in real-world experiments with these radios. One of the main problems is to ensure a sufficient RF performance of the front-end over a wide bandwidth. The thesis covers the analysis and mitigation of receiver non-linearity of typical direct-conversion receiver architectures, among other RF impairments. The main focus is on DSP-based algorithms for mitigating non-linearly induced interference, an approach also known as "Dirty RF" signal processing techniques. The conceived digital feedforward mitigation algorithm is verified through extensive simulations, RF measurements, and implementation in real hardware. Various studies are carried out that bridge the gap between theory and practical applicability of this approach, especially with the aim of integrating that technique into real devices. To this end, an advanced baseband behavioural model is developed that matches to direct-conversion receiver architectures as close as possible, and thus considers all generated distortions at RF and baseband. In addition, the algorithm's performance is verified under challenging fading conditions. Moreover, the thesis presents a resource-efficient real-time implementation of the proposed solution on an FPGA. Finally, different use cases are covered in the thesis that includes spectrum monitoring or sensing, GSM downlink reception, and GSM-based passive radar. It is shown that non-linear distortions can be successfully mitigated at system level in the digital domain, thereby decreasing the bit error rate of distorted modulated signals and reducing the amount of non-linearly induced interference. Finally, the effective linearity of the front-end is increased substantially. Thus, the proper operation of a low-cost radio under presence of receiver non-linearity is possible. Due to the flexible design, the algorithm is generally applicable for wideband receivers and is not restricted to software defined radios

Linearization of RF Power Amplifiers Using Adaptive Kalman Filtering Algorithm

International audienceIn this paper, a new linearization algorithm of Power Amplifier, based on Kalman filtering theory is proposed for obtaining fast convergence of the adaptive digital predistortion. The proposed method uses the real-time digital processing of baseband signals to compensate the nonlinearities and memory effects in radio-frequency Power Amplifier. To reduce the complexity of computing in classical Kalman Filtering, a sliding time-window has been inserted which combines off-line measurement and on-line parameter estimation with high sampling time to track the changes in the PA characteristics. We evaluated the performance of the proposed linearization scheme through simulation and experiments. Using digital signal processing, experimental results with commercial power amplifier are presented for multicarrier signals to demonstrate the effectiveness of this new approach

FEEDFORWARD ARTIFICIAL NEURAL NETWORK DESIGN UTILISING SUBTHRESHOLD MODE CMOS DEVICES

This thesis reviews various previously reported techniques for simulating artificial neural networks and investigates the design of fully-connected feedforward networks based on MOS transistors operating in the subthreshold mode of conduction as they are suitable for performing compact, low power, implantable pattern recognition systems. The principal objective is to demonstrate that the transfer characteristic of the devices can be fully exploited to design basic processing modules which overcome the linearity range, weight resolution, processing speed, noise and mismatch of components problems associated with weak inversion conduction, and so be used to implement networks which can be trained to perform practical tasks. A new four-quadrant analogue multiplier, one of the most important cells in the design of artificial neural networks, is developed. Analytical as well as simulation results suggest that the new scheme can efficiently be used to emulate both the synaptic and thresholding functions. To complement this thresholding-synapse, a novel current-to-voltage converter is also introduced. The characteristics of the well known sample-and-hold circuit as a weight memory scheme are analytically derived and simulation results suggest that a dummy compensated technique is required to obtain the required minimum of 8 bits weight resolution. Performance of the combined load and thresholding-synapse arrangement as well as an on-chip update/refresh mechanism are analytically evaluated and simulation studies on the Exclusive OR network as a benchmark problem are provided and indicate a useful level of functionality. Experimental results on the Exclusive OR network and a 'QRS' complex detector based on a 10:6:3 multilayer perceptron are also presented and demonstrate the potential of the proposed design techniques in emulating feedforward neural networks

Design of linear transmitters for wireless applications

Wireless standards for high data-rate communications typically employ complex modulation schemes that have large peak-to-average power ratios (PAPR), along with a significant bandwidth requirement. Transmitters for such applications often employ off-chip power amplifiers (PAs), that are typically operated in back-off, such that the peak output power is less than the output 1-dB compression point (P1dB), in order to minimize distortion. In mobile systems, architectures that can enhance the linearity of the transmit chain are highly attractive since these can reduce the PA's back-off requirement, which helps to enhance efficiency. In this dissertation, linearization techniques for mobile transmitters are explored. A Cartesian feedback-feedforward transmitter is proposed for linearity enhancement. The transmit path in the architecture is placed in a Cartesian feedback loop. The feedback error signal is applied to a Cartesian feedforward path for further linearity improvement. Linearity of the feedback-feedforward system is analyzed by using a Volterra series representation. System simulations using two-tone signals and modulated signals are also presented and are used to verify the linearity enhancement provided by the proposed architecture. A prototype transmitter IC that employs the Cartesian feedback-feedforward approach is implemented in a 0.13 μm CMOS process. Design considerations for critical transmitter circuits are discussed. A proof-of-concept Cartesian feedback-feedforward architecture that includes the prototype IC and external components is demonstrated. The implementation allows for a 8.7 dB improvement in the adjacent channel leakage ratio (ACLR), compared to an open-loop transmitter, for an output power of 16.6 dBm at 2.4 GHz while employing a 16-QAM LTE signal with 1.4 MHz bandwidth. The linearity of the Cartesian feedback-feedforward system is found to depend primarily on the loop gain of the Cartesian feedback and the linearity of the Cartesian feedforward path, which introduces a trade-off with power consumption. To enhance the linearity of the Cartesian feedback-feedforward transmitter even further within the Cartesian feedback loop, two modified Cartesian feedback-feedforward architectures are explored. System simulations show that both modified configurations can help to enhance linearity compared to the above Cartesian feedback-feedforward transmitter.Electrical and Computer Engineerin

Auxiliary-Path-Assisted Digital Linearization of Wideband Wireless Receivers

Wireless communication systems in recent years have aimed at increasing data rates by ensuring flexible and efficient use of the radio spectrum. The dernier cri in this field has been in the area of carrier aggregation and cognitive radio. Carrier aggregation is a major component of LTE-Advanced. With carrier aggregation, a number of separate LTE carriers can be combined, by mobile network operators, to increase peak data rates and overall network capacity. Cognitive radios, on the other hand, allow efficient spectrum usage by locating and using spatially vacant spectral bands. High monolithic integration in these application fields can be achieved by employing receiver architectures such as the wideband direct conversion receiver topology. This is advantageous from the view point of cost, power consumption and size. However, many challenges exist, of particular importance is nonlinear distortion arising from analog front-end components such as low noise amplifiers (LNA). Nonlinear distortions especially become severe when several signals of varying amplitudes are received simultaneously. In such cases, nonlinear distortions stemming from strong signals may deteriorate the reception of the weaker signals, and also impair the receiver’s spectrum sensing capabilities. Nonlinearity, usually a consequence of dynamic range limitation, degrades performance in wideband multi-operator communications systems, and it will have a notable role in future wireless communication system design. This thesis presents a digital domain linearization technique that employs a very nonlinear auxiliary receiver path for nonlinear distortion cancellation. The proposed linearization technique relies on one-time adaptively-determined linearization coefficients for cancelling nonlinear distortions. Specifically, we take a look at canceling the troublesome in-band third order intermodulation products using the proposed technique. The proposed technique can be extended to cancel out both even and higher order odd intermodulation products. Dynamic behavioral models are used to account for RF nonlinearities, including memory effects which cannot be ignored in the wideband scenario. Since the proposed linearization technique involves the use of two receiver paths, techniques for correcting phase delays between the two paths are also introduced. Simplicity is the hallmark of the proposed linearization technique. It can achieve up to +30 dBm in IIP3 performance with ADC resolution being a major performance bottleneck. It also shows strong tolerance to strong blocker nonlinearities

Strategies for enhancing DC gain and settling performance of amplifiers

The operational amplifier (op amp) is one of the most widely used and important building blocks in analog circuit design. High gain and high speed are two important properties of op amps because they determine the settling behavior of the op amps. As supply voltages decrease, the realization of high gain amplifiers with large Gain-Bandwidth-Products (GBW) has become challenging. The major focus in this dissertation is on the negative output impedance gain enhancement technique. The negative impedance gain enhancement technique offers potential for achieving very high gain and energy-efficient fast settling and is low-voltage compatible. Misconceptions that have limited the practical adoption of this gain enhancement technique are discussed. A new negative conductance gain enhancement technique was proposed. The proposed circuit generates a negative conductance with matching requirements for achieving very high DC gain that are less stringent than those for existing -g m gain enhancement schemes. The proposed circuit has potential for precise digital control of a very large DC gain. A prototype fully differential CMOS operational amplifier was designed and fabricated based on the proposed gain enhancement technique. Experimental results which showed a DC gain of 85dB and an output swing of 876mVp-p validated the fundamental performance characteristics of this technique. In a separate section, a new amplifier architecture with bandpass feedforward compensation is presented. It is shown that a bandpass feedforward path can be used to substantially extend the unity-gain-frequency of an operational amplifier. Simulation results predict significant improvements in rise time and settling performance and show that the bandpass compensation scheme is reasonably robust. In the final section, a new technique for asynchronous data recovery based upon using a delay line in the incoming data path is introduced. The proposed data recovery system is well suited for tight tolerance channels and coding systems supporting standards that limit the maximum number of consecutive 0\u27s and 1\u27s in a data stream. This system does not require clock recovery, suffers no loss of data during acquisition, has a reduced sensitivity to jitter in the incoming data and does not exhibit jitter enhancement associated with VCO tracking in a PLL