Low power digital baseband core for wireless Micro-Neural-Interface using CMOS sub/near-threshold circuit

This thesis presents the work on designing and implementing a low power digital baseband core with custom-tailored protocol for wirelessly powered Micro-Neural-Interface (MNI) System-on-Chip (SoC) to be implanted within the skull to record cortical neural activities. The core, on the tag end of distributed sensors, is designed to control the operation of individual MNI and communicate and control MNI devices implanted across the brain using received downlink commands from external base station and store/dump targeted neural data uplink in an energy efficient manner. The application specific protocol defines three modes (Time Stamp Mode, Streaming Mode and Snippet Mode) to extract neural signals with on-chip signal conditioning and discrimination. In Time Stamp Mode, Streaming Mode and Snippet Mode, the core executes basic on-chip spike discrimination and compression, real-time monitoring and segment capturing of neural signals so single spike timing as well as inter-spike timing can be retrieved with high temporal and spatial resolution. To implement the core control logic using sub/near-threshold logic, a novel digital design methodology is proposed which considers INWE (Inverse-Narrow-Width-Effect), RSCE (Reverse-Short-Channel-Effect) and variation comprehensively to size the transistor width and length accordingly to achieve close-to-optimum digital circuits. Ultra-low-power cell library containing 67 cells including physical cells and decoupling capacitor cells using the optimum fingers is designed, laid-out, characterized, and abstracted. A robust on-chip sense-amp-less SRAM memory (8X32 size) for storing neural data is implemented using 8T topology and LVT fingers. The design is validated with silicon tapeout and measurement shows the digital baseband core works at 400mV and 1.28 MHz system clock with an average power consumption of 2.2 μW, resulting in highest reported communication power efficiency of 290Kbps/μW to date

A novel deep submicron bulk planar sizing strategy for low energy subthreshold standard cell libraries

Engineering andPhysical Science ResearchCouncil (EPSRC) and Arm Ltd for providing funding in the form of grants and studentshipsThis work investigates bulk planar deep submicron semiconductor physics in an attempt to improve standard cell libraries aimed at operation in the subthreshold regime and in Ultra Wide Dynamic Voltage Scaling schemes. The current state of research in the field is examined, with particular emphasis on how subthreshold physical effects degrade robustness, variability and performance. How prevalent these physical effects are in a commercial 65nm library is then investigated by extensive modeling of a BSIM4.5 compact model. Three distinct sizing strategies emerge, cells of each strategy are laid out and post-layout parasitically extracted models simulated to determine the advantages/disadvantages of each. Full custom ring oscillators are designed and manufactured. Measured results reveal a close correlation with the simulated results, with frequency improvements of up to 2.75X/2.43X obs erved for RVT/LVT devices respectively. The experiment provides the first silicon evidence of the improvement capability of the Inverse Narrow Width Effect over a wide supply voltage range, as well as a mechanism of additional temperature stability in the subthreshold regime. A novel sizing strategy is proposed and pursued to determine whether it is able to produce a superior complex circuit design using a commercial digital synthesis flow. Two 128 bit AES cores are synthesized from the novel sizing strategy and compared against a third AES core synthesized from a state-of-the-art subthreshold standard cell library used by ARM. Results show improvements in energy-per-cycle of up to 27.3% and frequency improvements of up to 10.25X. The novel subthreshold sizing strategy proves superior over a temperature range of 0 °C to 85 °C with a nominal (20 °C) improvement in energy-per-cycle of 24% and frequency improvement of 8.65X. A comparison to prior art is then performed. Valid cases are presented where the proposed sizing strategy would be a candidate to produce superior subthreshold circuits

Design of a RF communication receiver front-end for ultra-low power and voltage applications in a FDSOI 28nm technology

The advances in the semiconductor and wireless industry have enabled the expansion of new paradigms, which have given rise to concepts like Internet of Things (IoT). Apart from qualities like size, speed or cost, the ever-increasing demand for autonomy focuses all design efforts in the minimization of power consumption. Scaling technologies and the request to reduce power consumption have pushed designers towards lower supply voltages. Despite the fact that technology scalability allows for faster transistors, radio-frequency (RF) integrated circuit (IC) design accuses the reduction of the voltage supply through frequency response degradation, which significantly deteriorates the overall performance. Analog and RF circuits in highend applications require substantial gate voltage overdrive to maintain device speed, which further complicates the design due to the reduction of voltage headroom. As a consequence, the necessity to develop circuit topologies capable to deal with low-power and low-voltage stringent constraints well suited to applications requiring long battery life and low cost emerges. This work aims to implement a low-noise amplifier and mixer stages of a radio-frequency receiver front-end working under an ultra-low power (< 100 ?W) and ultra-low voltage (< 0.8V) scenario while targeting decent overall performance. To cope with the stringent power requirements, 28nm FD-SOI technology will be used to take maximum profit of aggressive forward body bias and enhance transistor performance

Design and Implementation of a Low Power T-gate Cell Library and Comparison with Its Cmos Equivalent

This work presents the design methodologies, considerations and practical implementation techniques of a sub-threshold/ moderate inversion variability aware Transmission Gate based digital cell library. The implementation method of a reduced ASIC cell library containing minimum number of logic gates sufficient for further front end and back end processing is described. The proposed library targets a reduced implementation time and effort suitable for academic and industrial environment aiming minimum power consumption in battery less devices, portable electronic gadgets or wireless micro sensor networks where computation speed is not of prime concern. To the authors best knowledge, none of the literature till date demonstrates clearly and in a consolidated manner the applicability of T-Gate logic topology as a candidate for ultra-low power applications. Hence, a comparison is presented with equivalent low power CMOS logic gates. Circuit behavior can be significantly impacted due to MOSFET parameter variation. Clear simulation based measurement techniques are presented for measuring concerned parameters like input capacitance, Static Noise Margin(SNM) and IOFF of the T-Gate logic cells and compared with its CMOS equivalent at the same PVT corners. It is observed that the T-Gate shows lower normalized input capacitance than CMOS logic gates. A statistical analysis of logic failure is also presented along with its potential solutions for improvement. As compared to the CMOS gates, the T-Gate logic gates are found to demonstrate slightly narrower distribution of the switching threshold point(VTrip) when performed 200 point Monte Carlo simulation taking process variation and mismatch into account. The CMOS gates demonstrate better static noise margin and hence more robust than T-Gate logic cell and suitable for lower supply voltage operation. A comparison of IOFF is presented to compare the static behavior of the two topologies. The details of device and gate sizing methodology are described along with necessary references. The library is characterized and abstracted to generate necessary files for further processing. A target system is synthesized and a seven stage ring oscillator is simulated in both topologies and is compared to make conclusion based on the observations. T-Gate logic cells demonstrate better static behavior but outperformed by its CMOS logic equivalent in terms of energy consumed per cycle within the range of VDDD from 400mV to 600mV. T-Gate logic gates are slower than its CMOS counterpart at any VDDD of operation and insignificant improvement is achieved with increasing power supply.Electrical Engineerin

III-V Nanowire MOSFET High-Frequency Technology Platform

This thesis addresses the main challenges in using III-V nanowireMOSFETs for high-frequency applications by building a III-Vvertical nanowire MOSFET technology library. The initial devicelayout is designed, based on the assessment of the current III-V verticalnanowire MOSFET with state-of-the-art performance. The layout providesan option to scale device dimensions for the purpose of designing varioushigh-frequency circuits. The nanowire MOSFET device is described using1D transport theory, and modeled with a compact virtual source model.Device assessment is performed at high frequencies, where sidewall spaceroverlaps have been identified and mitigated in subsequent design iterations.In the final stage of the design, the device is simulated with fT > 500 GHz,and fmax > 700 GHz.Alongside the III-V vertical nanowire device technology platform, adedicated and adopted RF and mm-wave back-end-of-line (BEOL) hasbeen developed. Investigation into the transmission line parameters revealsa line attenuation of 0.5 dB/mm at 50 GHz, corresponding to state-ofthe-art values in many mm-wave integrated circuit technologies. Severalkey passive components have been characterized and modeled. The deviceinterface module - an interconnect via stack, is one of the prominentcomponents. Additionally, the approach is used to integrate ferroelectricMOS capacitors, in a unique setting where their ferroelectric behavior iscaptured at RF and mm-wave frequencies.Finally, circuits have been designed. A proof-of-concept circuit, designedand fabricated with III-V lateral nanowire MOSFETs and mm-wave BEOL, validates the accuracy of the BEOL models, and the circuit design. Thedevice scaling is shown to be reflected into circuit performance, in aunique device characterization through an amplifier noise-matched inputstage. Furthermore, vertical-nanowire-MOSFET-based circuits have beendesigned with passive feedback components that resonate with the devicegate-drain capacitance. The concept enables for device unilateralizationand gain boosting. The designed low-noise amplifiers have matching pointsindependent on the MOSFET gate length, based on capacitance balancebetween the intrinsic and extrinsic capacitance contributions, in a verticalgeometry. The proposed technology platform offers flexibility in device andcircuit design and provides novel III-V vertical nanowire MOSFET devicesand circuits as a viable option to future wireless communication systems

Designing energy-efficient sub-threshold logic circuits using equalization and non-volatile memory circuits using memristors

The very large scale integration (VLSI) community has utilized aggressive complementary metal-oxide semiconductor (CMOS) technology scaling to meet the ever-increasing performance requirements of computing systems. However, as we enter the nanoscale regime, the prevalent process variation effects degrade the CMOS device reliability. Hence, it is increasingly essential to explore emerging technologies which are compatible with the conventional CMOS process for designing highly-dense memory/logic circuits. Memristor technology is being explored as a potential candidate in designing non-volatile memory arrays and logic circuits with high density, low latency and small energy consumption. In this thesis, we present the detailed functionality of multi-bit 1-Transistor 1-memRistor (1T1R) cell-based memory arrays. We present the performance and energy models for an individual 1T1R memory cell and the memory array as a whole. We have considered TiO2- and HfOx-based memristors, and for these technologies there is a sub-10% difference between energy and performance computed using our models and HSPICE simulations. Using a performance-driven design approach, the energy-optimized TiO2-based RRAM array consumes the least write energy (4.06 pJ/bit) and read energy (188 fJ/bit) when storing 3 bits/cell for 100 nsec write and 1 nsec read access times. Similarly, HfOx-based RRAM array consumes the least write energy (365 fJ/bit) and read energy (173 fJ/bit) when storing 3 bits/cell for 1 nsec write and 200 nsec read access times. On the logic side, we investigate the use of equalization techniques to improve the energy efficiency of digital sequential logic circuits in sub-threshold regime. We first propose the use of a variable threshold feedback equalizer circuit with combinational logic blocks to mitigate the timing errors in digital logic designed in sub-threshold regime. This mitigation of timing errors can be leveraged to reduce the dominant leakage energy by scaling supply voltage or decreasing the propagation delay. At the fixed supply voltage, we can decrease the propagation delay of the critical path in a combinational logic block using equalizer circuits and, correspondingly decrease the leakage energy consumption. For a 8-bit carry lookahead adder designed in UMC 130 nm process, the operating frequency can be increased by 22.87% (on average), while reducing the leakage energy by 22.6% (on average) in the sub-threshold regime. Overall, the feedback equalization technique provides up to 35.4% lower energy-delay product compared to the conventional non-equalized logic. We also propose a tunable adaptive feedback equalizer circuit that can be used with sequential digital logic to mitigate the process variation effects and reduce the dominant leakage energy component in sub-threshold digital logic circuits. For a 64-bit adder designed in 130 nm our proposed approach can reduce the normalized delay variation of the critical path delay from 16.1% to 11.4% while reducing the energy-delay product by 25.83% at minimum energy supply voltage. In addition, we present detailed energy-performance models of the adaptive feedback equalizer circuit. This work serves as a foundation for the design of robust, energy-efficient digital logic circuits in sub-threshold regime

Optimization studies of thermal bimorph cantilevers, electrostatic torsion actuators and variable capacitors

In this dissertation, theoretical analyses and optimization studies are given for three kinds of MEMS devices: thermal bimorph cantilevers, electrostatic torsion actuators, and variable capacitors. Calculation, simulation, and experimental data are used to confirm the device behavior and demonstrate the application of the design approaches. For thermal bimorph cantilevers, an analytical model is presented which allows theoretical analysis and quantitative optimization of the performance based on material properties and device dimensions. Bimorph cantilevers are divided into two categories for deflection optimization: either the total thickness is constant, or the cantilever has one constant and one variable layer thickness. The optimum equations are then derived for each case and can be used as design rules. The results show that substantial improvements are possible over existing design approaches. Other parameters like static temperature distribution, power consumption, and dynamic behavior are also discussed, as are design tradeoffs such as feature size, application constraints, fabrication feasibility, and cost. The electrostatic torsion actuator studies are conducted for two device types: round and rectangular. The first case describes an analytical study of the pull-in effect in round, double-gimbaled, electrostatic torsion actuators with buried, variable length electrodes, designed for optical cross-connect applications. It is found that the fractional tilt at pull-in for the inner round plate in this system depends only on the ratio of the length of the buried electrode to the radius of the plate. The fractional tilt at pull-in for the outer support ring depends only on the ratio of the length of the buried electrode to the outer radius of the ring and the ratio of the ring\u27s inner and outer radii. Expressions for the pull-in voltage are determined in both cases. General relationships are also derived relating the applied voltage to the resulting tilt angle, both normalized by their pull-in values. Calculated results are verified by comparison with finite element MEMCAD simulations, with fractional difference smaller than 4% for torsion mode dominant systems. For the second case, a fast, angle based design approach for rectangular electrostatic torsion actuators based on several simple equations is developed. This approach is significantly more straightforward than the usual full calculation or simulation methods. The main results of the simplified approach are verified by comparing them with analytical calculations and MEMCAD simulations with fractional difference smaller than 3% for torsion mode dominant actuators. Also, good agreement is found by comparison with the measured behavior of a micro-fabricated full-plate device. In the last topic, ultra-thin silicon wafers, SU-8 bonding and deep reactive ion etching technology have been combined for the fabrication of folded spring, dual electrostatic drive, vertical plate variable capacitor devices with displacement limiting bumpers. Due to the presence of the bumpers, the variable capacitor with parallel plate drive electrodes has two tuning voltage regimes: first a parabolic region that achieves roughly a 290% tuning range, then a linear region that achieves an additional 310%, making the total tuning range about 600%. The variable capacitor with comb drive electrodes has a parabolic region that achieves roughly a 205% tuning range, then a linear region that achieves an additional 37%, making its total tuning range about 242%. The variable capacitors have Q factors around 100 owing to the use of silicon electrodes other than lower resistivity metal

NASA SBIR abstracts of 1991 phase 1 projects

The objectives of 301 projects placed under contract by the Small Business Innovation Research (SBIR) program of the National Aeronautics and Space Administration (NASA) are described. These projects were selected competitively from among proposals submitted to NASA in response to the 1991 SBIR Program Solicitation. The basic document consists of edited, non-proprietary abstracts of the winning proposals submitted by small businesses. The abstracts are presented under the 15 technical topics within which Phase 1 proposals were solicited. Each project was assigned a sequential identifying number from 001 to 301, in order of its appearance in the body of the report. Appendixes to provide additional information about the SBIR program and permit cross-reference of the 1991 Phase 1 projects by company name, location by state, principal investigator, NASA Field Center responsible for management of each project, and NASA contract number are included