Exploration of operator method digital optical computers for application to NASA

Digital optical computer design has been focused primarily towards parallel (single point-to-point interconnection) implementation. This architecture is compared to currently developing VHSIC systems. Using demonstrated multichannel acousto-optic devices, a figure of merit can be formulated. The focus is on a figure of merit termed Gate Interconnect Bandwidth Product (GIBP). Conventional parallel optical digital computer architecture demonstrates only marginal competitiveness at best when compared to projected semiconductor implements. Global, analog global, quasi-digital, and full digital interconnects are briefly examined as alternative to parallel digital computer architecture. Digital optical computing is becoming a very tough competitor to semiconductor technology since it can support a very high degree of three dimensional interconnect density and high degrees of Fan-In without capacitive loading effects at very low power consumption levels

Form and Data - from linear Calculus to cybernetic Computation and Interaction

Digital architecture developed in the 1960s and, supported by CAAD the 1990s, has created the path towards an architecture produced by computer and architect in a mutual relationship. The evolution of architecture since the 1970s led to the beginning of the first digital turn in the 1990s, and subsequently to the emergence of new typologies of buildings, architects and design tools; atom-based, bit-based (virtual) [1], and cyber-physical as a combination of both. The paper provides an insight into historical foundations of CAAD insofar as it engages with complexity in mechanics, geometry, and space between the 1600s and 1950s. I will address a selection of principles discovered, and mechanisms invented before computer-aided-architectural-design; those include the typewriter, the Cartesian grid and a pre-cyber-physical system by Hermann von Helmholtz. The paper concludes with a summary and an outlook to the future of CAAD challenged by the variety of correlations of disparate data sets

CORDIC Based Array Architecture for Affine Transformation of Images

In this paper a multiplierless array architecture of Affine transformation is proposed. The array architecture utilizes CoOrdinate Rotation DIgital Computer (CORDIC) arithmetic unit as the basic Processing Element (PE). To construct the architecture two types of CORDIC units viz. the circular and linear are used. The architecture is flexible and can be configured according to the specification of the user. Due to its multiplierless organization the array architecture is expected to consume less silicon area and power compared to that of the multiplier-based designs

A direct-execution parallel architecture for the Advanced Continuous Simulation Language (ACSL)

A direct-execution parallel architecture for the Advanced Continuous Simulation Language (ACSL) is presented which overcomes the traditional disadvantages of simulations executed on a digital computer. The incorporation of parallel processing allows the mapping of simulations into a digital computer to be done in the same inherently parallel manner as they are currently mapped onto an analog computer. The direct-execution format maximizes the efficiency of the executed code since the need for a high level language compiler is eliminated. Resolution is greatly increased over that which is available with an analog computer without the sacrifice in execution speed normally expected with digitial computer simulations. Although this report covers all aspects of the new architecture, key emphasis is placed on the processing element configuration and the microprogramming of the ACLS constructs. The execution times for all ACLS constructs are computed using a model of a processing element based on the AMD 29000 CPU and the AMD 29027 FPU. The increase in execution speed provided by parallel processing is exemplified by comparing the derived execution times of two ACSL programs with the execution times for the same programs executed on a similar sequential architecture

The Design of a System Architecture for Mobile Multimedia Computers

This chapter discusses the system architecture of a portable computer, called Mobile Digital Companion, which provides support for handling multimedia applications energy efficiently. Because battery life is limited and battery weight is an important factor for the size and the weight of the Mobile Digital Companion, energy management plays a crucial role in the architecture. As the Companion must remain usable in a variety of environments, it has to be flexible and adaptable to various operating conditions. The Mobile Digital Companion has an unconventional architecture that saves energy by using system decomposition at different levels of the architecture and exploits locality of reference with dedicated, optimised modules. The approach is based on dedicated functionality and the extensive use of energy reduction techniques at all levels of system design. The system has an architecture with a general-purpose processor accompanied by a set of heterogeneous autonomous programmable modules, each providing an energy efficient implementation of dedicated tasks. A reconfigurable internal communication network switch exploits locality of reference and eliminates wasteful data copies