Novel arithmetic implementations using cellular neural network arrays.

The primary goal of this research is to explore the use of arrays of analog self-synchronized cells---the cellular neural network (CNN) paradigm---in the implementation of novel digital arithmetic architectures. In exploring this paradigm we also discover that the implementation of these CNN arrays produces very low system noise; that is, noise generated by the rapid switching of current through power supply die connections---so called di/dt noise. With the migration to sub 100 nanometer process technology, signal integrity is becoming a critical issue when integrating analog and digital components onto the same chip, and so the CNN architectural paradigm offers a potential solution to this problem. A typical example is the replacement of conventional digital circuitry adjacent to sensitive bio-sensors in a SoC Bio-Platform. The focus of this research is therefore to discover novel approaches to building low-noise digital arithmetic circuits using analog cellular neural networks, essentially implementing asynchronous digital logic but with the same circuit components as used in analog circuit design. We address our exploration by first improving upon previous research into CNN binary arithmetic arrays. The second phase of our research introduces a logical extension of the binary arithmetic method to implement binary signed-digit (BSD) arithmetic. To this end, a new class of CNNs that has three stable states is introduced, and is used to implement arithmetic circuits that use binary inputs and outputs but internally uses the BSD number representation. Finally, we develop CNN arrays for a 2-dimensional number representation (the Double-base Number System - DBNS). A novel adder architecture is described in detail, that performs the addition as well as reducing the representation for further processing; the design incorporates an innovative self-programmable array. Extensive simulations have shown that our new architectures can reduce system noise by almost 70dB and crosstalk by more than 23dB over standard digital implementations.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2005 .I27. Source: Dissertation Abstracts International, Volume: 66-11, Section: B, page: 6159. Thesis (Ph.D.)--University of Windsor (Canada), 2005

VLSI library cells for cellular neural network applications.

Cellular Neural Networks (CNNs) are massively parallel nonlinear locally connected analog cells; they are often targeted for use in image processing applications. An analog signal processor which (in majority of cases) does not require A/D conversion, occupies only a fraction of the area occupied by its digital counterpart. In image processing, it is possible to integrate an analog processor with each signal source (pixel) without leading to impractically low signal-source (or pixel) density. This makes possible the parallel loading or injecting of the input signal into the analog processor. Thus, sequential sampling at the output voltage (or current) of each signal-source is eliminated and a high degree of parallelism in signal processing is easily achievable. With the use of modified and creative algorithms, Cellular Neural Networks may also be used for digital arithmetic operations. For the same speed, these analog processors have lower slew rates compared to their digital counterparts which, in turn, leads to a lower generated noise. Using a Cellular Neural Network architecture, this thesis focuses on silicon implementation and experimental characterization of the building blocks for image processing and binary arithmetic applications using the MOSIS 0.5mum technology. These library cells are verified functionally at the layout level by conducting DRC, LVS, and post layout simulations. Sensitivity analysis is also carried out on a basic CNN cell in order to determine its tolerance with respect to expected variations in process parameters.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1997 .M38. Source: Masters Abstracts International, Volume: 39-02, page: 0565. Adviser: G. A. Jullien. Thesis (M.A.Sc.)--University of Windsor (Canada), 1998

A Bio-Inspired Two-Layer Mixed-Signal Flexible Programmable Chip for Early Vision

A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the visual pathway, what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5 μm CMOS. It renders a computing power per silicon area and power consumption that is amongst the highest reported for a single chip. The details of the bio-inspired network model, the analog building block design challenges and trade-offs and some functional tests results are presented in this paper.Office of Naval Research (USA) N-000140210884European Commission IST-1999-19007Ministerio de Ciencia y Tecnología TIC1999-082

Optical computing: introduction by the guest editors to the feature in the 1 May 1988 issue

The feature in the 1 May 1988 issue of Applied Optics includes a collection of papers originally presented at the 1987 Lake Tahoe Topical Meeting on Optical Computing. These papers emphasize digital optical computing systems, optical interconnects, and devices for optical computing, but analog optical processing is considered as well

Programmable retinal dynamics in a CMOS mixed-signal array processor chip

The low-level image processing that takes place in the retina is intended to compress the relevant visual information to a manageable size. The behavior of the external layers of the biological retina has been successfully modelled by a Cellular Neural Network, whose evolution can be described by a set of coupled nonlinear differential equations. A mixed-signal VLSI implementation of the focal-plane low-level image processing based upon this biological model constitutes a feasible and cost effective alternative to conventional digital processing in real-time applications. For these reasons, a programmable array processor prototype chip has been designed and fabricated in a standard 0.5μm CMOS technology. The integrated system consists of a network of two coupled layers, containing 32 × 32 elementary processors, running at different time constants. Involved image processing algorithms can be programmed on this chip by tuning the appropriate interconnections weights. Propagative, active wave phenomena and retina-like effects can be observed in this chip. Design challenges, trade-offs, the buildings blocks and some test results are presented in this paper.Office of Naval Research (USA) N00014-00-10429European Community IST-1999-19007Ministerio de Ciencia y Tecnología TIC1999-082