Digitally-Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative “iterative” harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and 3.5 dBm in-band IIP3 while the out-of-band IIP3 is + 16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply

Multi-tap Digital Canceller for Full-Duplex Applications

We identify phase noise as a bottleneck for the performance of digital self-interference cancellers that utilize a single auxiliary receiver---single-tap digital cancellers---and operate in multipath propagation environments. Our analysis demonstrates that the degradation due to phase noise is caused by a mismatch between the analog delay of the auxiliary receiver and the different delays of the multipath components of the self-interference signal. We propose a novel multi-tap digital self-interference canceller architecture that is based on multiple auxiliary receivers and a customized Normalized-Least-Mean-Squared (NLMS) filtering for self-interference regeneration. Our simulation results demonstrate that our proposed architecture is more robust to phase noise impairments and can in some cases achieve 10~dB larger self-interference cancellation than the single-tap architecture.Comment: SPAWC 201

Efficient DSP and Circuit Architectures for Massive MIMO: State-of-the-Art and Future Directions

Massive MIMO is a compelling wireless access concept that relies on the use of an excess number of base-station antennas, relative to the number of active terminals. This technology is a main component of 5G New Radio (NR) and addresses all important requirements of future wireless standards: a great capacity increase, the support of many simultaneous users, and improvement in energy efficiency. Massive MIMO requires the simultaneous processing of signals from many antenna chains, and computational operations on large matrices. The complexity of the digital processing has been viewed as a fundamental obstacle to the feasibility of Massive MIMO in the past. Recent advances on system-algorithm-hardware co-design have led to extremely energy-efficient implementations. These exploit opportunities in deeply-scaled silicon technologies and perform partly distributed processing to cope with the bottlenecks encountered in the interconnection of many signals. For example, prototype ASIC implementations have demonstrated zero-forcing precoding in real time at a 55 mW power consumption (20 MHz bandwidth, 128 antennas, multiplexing of 8 terminals). Coarse and even error-prone digital processing in the antenna paths permits a reduction of consumption with a factor of 2 to 5. This article summarizes the fundamental technical contributions to efficient digital signal processing for Massive MIMO. The opportunities and constraints on operating on low-complexity RF and analog hardware chains are clarified. It illustrates how terminals can benefit from improved energy efficiency. The status of technology and real-life prototypes discussed. Open challenges and directions for future research are suggested.Comment: submitted to IEEE transactions on signal processin

Architectures for RF Frequency synthesizers

Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products.\ud Written for:\ud Electrical and electronic engineer

Receiver architecture of the thousand-element array (THEA)

As part of the development of a new international radio-telescope SKA (Square Kilometre Array), an outdoor phasedarray prototype, the THousand Element Array (THEA), is being developed at NFRA. THEA is a phased array with 1024 active elements distributed on a regular grid over a surface of approximately 16 m2. The array is organised into 16 units denoted as tiles. THEA operates in the frequency band from 750 to 1500 MHz.\ud On a tile the signals from 64 antenna elements are converted into two independent RF beams. Two times 16 beams can be made simultaneously with full sensitivity by the real-time digital beam former of the THEA system. At the output of each tile the analog RF signal from a beam is converted into a 2 × 12-bit digital quadrature representation by a receiver system.\ud A double super-heterodyne architecture is used to mix the signal band of interest to an intermediate frequency of 210 MHz. The IF-signal is shifted to baseband by means of a partly digitally implemented I/Q mixer scheme. After a quadrature mixer stage, the I and Q signals are digitised by means of 12 bit A/D converters at 40 MS/s. Implementing a part of the mixing scheme digitally offers the flexibility to use different I/Q architectures, e.g. Hartley and Weaver mixer setups. This way the effect of RFI in different mixing architectures can be analyzed. After the digital processing, the samples are multiplexed, serialised and transported over fibres to the central adaptive digital beam former unit where the signals from all tiles are combined giving 32 beams.\ud This paper focuses on the design choices and the final implementation of the THEA system. In particular, the receiver architecture is addressed. A digital solution is presented, which enables switching between a Hartley and a Weaver based mixer scheme

An adaptive digital caliration of multi-step A/D converters.

A novel digital technique for efficient calibration of static errors in high-speed, high-resolution, multi-step ADCs is proposed. The parameter update within the calibration method is extended to include and correct effects of temperature and process variations. Additionally, to guide the verification process with the information obtained through monitoring process variations, expectation-maximization method is employed. The algorithm is evaluated on a prototype multi-step ADC converter with embedded dedicated sensors fabricated in standard single poly, six metal 0.09-樨 CMOS