NANOPOROUS AAO: A PLATFORM FOR REGULAR HETEROGENEOUS NANOSTRUCTURES AND ENERGY STORAGE DEVICES

Nanoporous anodic aluminum oxide (AAO) has vast implications as a tool for nanoscience research and as a nanostructure in which nanoscale devices can be fabricated because of its regular and ordered nanopores. Self-assembly plays a critical role in pore ordering, causing nanopores to grow parallel with one another in high density. The mild electrochemical conditions in which porous AAO grows along with its relatively cheap starting materials makes this nanomaterial a cost effective alternative to advanced photolithography techniques for forming high surface area nanostructures over large areas. In this research, atomic layer deposition (ALD) was used to deposit conformal films within in nanoporous AAO with hopes to 1) develop methodologies to characterize ALD depositions within its high aspect ratio nanopores and 2) to better understand how to use nanoporous AAO templates as a scaffold for energy devices, specifically Metal-Insulator-Metal (MIM) capacitors. Using the nanotube template synthesis method, ALD films were deposited onto nanoporous AAO, later removing the films deposited within the templates nanopores for characterization in TEM. This nanotube metrology characterization involves first obtaining images of full length ALD-AAO nanotubes, and then measuring wall thickness as a function of depth within the nanopore. MIM nanocapacitors were also constructed in vertical AAO nanopores by deposition of multilayer ALD films. MIM stacks were patterned into micro-scale capacitors for electrical characterization

Novel 3-D IC technology

textFor many decades silicon based CMOS technology has made continual increase in drive current to achieve higher speed and lower power by scaling the gate length and the gate insulator thickness. The scaling becomes increasingly challenging because the devices are approaching physical quantum limits. Three-dimensional electronic devices, such as double gate, tri-gate and nanowire field-effect-transistors (FETs) provide an alternative solution because the ultra-thin fin or nanowire provides better electrostatic control of the device channel. Also high-[kappa] oxides lower the gate leakage current significantly, due to larger thickness for the same equivalent oxide thickness (EOT) compared with SiO₂ beyond the 22 nm node. Moreover, metal gate that avoids the poly-depletion effect in poly-Si gate has become mainstream semiconductor technology. The enabler technologies for high-[kappa] / metal gate 3D transistors include fabrication of high quality, vertical nanowire arrays, conformal metal and dielectric deposition and vertical patterning. One of the main focuses of this dissertation is developing a fabrication process flow to realize high performance MOSFETs with high-[kappa] oxide and metal gate on vertical silicon nanowire arrays. A variety of approaches to fabricating highly ordered silicon nanowire arrays have been achieved. Deep silicon etching process was developed and optimized for nanowire FETs. Process integration and patterning mythologies for high-[kappa] / metal gate were investigated and accomplished. 3-D electronic devices including nanowire capacitors, nanowire FETs and double gate MOSFETs for power applications were fabricated and characterized. The second part of this dissertation is about flexible electronics. Mechanically flexible integrated circuits (ICs) have gained increasing attention in recent years with emerging markets in portable electronics. Although a number of thin-film-transistor (TFT) IC solutions have been reported, challenges still remain for fabrication of inexpensive, high performance flexible devices. We report a simple and straightforward solution: mechanically exfoliating a thin Si film containing ICs. Transistors and circuits can be pre-fabricated on bulk silicon wafer with conventional CMOS process flow without additional temperature or process limitations. The short channel MOSFETs exhibit similar electrical performance before and after exfoliation. This exfoliation process also provides a fast and economical approach to produce thinned silicon wafers, which is a key enabler for three-dimensional (3D) silicon integration based on Through Silicon Vias (TSVs).Electrical and Computer Engineerin

Electrical properties of ultra thin Al2O3 and HfO2 films as gate dielectrics in MOS technology

The rapidly evolving silicon industry demands devices with high-speed and low power consumption. This has led to aggressive scaling of the dimensions in metal oxide semiconductor field effect transistors (MOSFETs). The channel length has been reduced as a result of this scaling. The industry favorite, SlO2, has reached limitations in the thickness regime of 1-1.5 nm as a gate dielectric. High-κ gate dielectrics such as Al203 and HfO2 and their silicates are some of the materials that may, probably, replace SlO2, as gate dielectric in the next four to five years. The present study is an attempt to understand the electrical characteristics of these exciting materials grown by atomic layer deposition (ALD) technique. The flat band voltages (VFB) were determined from C-V measurements on circularly patterned MOS capacitors. For phosphorous doped polysilicon electrodes and Al-oxide based dielectrics, positive shifts in VFB were observed, relative to a pure SlO2 control, ranging from 0.2 to 0.8V. It is believed that this is caused by fixed charges. Rapid thermal annealing at 1000°C tends to decrease VFB relative to a 800°C anneal. Changes in VFB UP to 0.35 V are observed for films deposited over SlO2 underlayers, while smaller changes, up to 0.05 V, are observed for films deposited directly on Si. Spike annealing is also observed to reduce oxide leakage. HfO2 showed large amount of leakage resulting in difficulty in performing capacitance measurements. ZrO2 was found to be reacting with polycrystalline silicon and thus high leakage current was observed

Atomic Layer Deposition and Performance of ZrO2-Al2O3 Thin Films

Thin mixed and nanolaminate films of ZrO2 and Al2O3 were grown by atomic layer deposition from the corresponding metal chlorides and water. The films were grown at 350 degrees C in order to ensure ZrO2 crystallization in the as-deposited state. The relative thicknesses of layers in the structure of the nanolaminates were controlled in order to maximize the content of metastable polymorphs of ZrO2 that have higher permittivity than that of the stable monoclinic ZrO2 . The multilayer films demonstrated interfacial charge polarization and saturative magnetization in external fields. The conductivity of the films could be switched between high and low resistance states by applying voltages of alternating polarity. (C) 2018 The Electrochemical Society.Peer reviewe

A Study of Ozone as an Oxygen Source for the Growth of High-Κ Dielectric Films for Gate Dielectric on GaN/AlGaN/GaN

GaN is a promising alternative to silicon technology for the next-generation high-power and high-frequency electronics. The choice stems from the intrinsic properties of GaN of a wide bandgap and consequently high breakdown voltage, high saturation electron velocity and good thermal conductivity. Spontaneous and piezoelectric polarization effects cause accumulation of a high density of carriers at III-Nitride heterointerfaces enabling engineering of high mobility channels. The primary factor inhibiting the further growth of GaN HEMTs is the high leakage current leading to device unreliability. The MIS-structure used in Si-CMOS processing has been adapted and shown to reduce leakage current in GaN technology. However, the introduction of an insulator adds another interface which suffers from poor quality due to innumerable traps with varying time constants. This leads to device threshold voltage instability and drain current collapse, while decreasing the device transconductance due to the increased gate-to-channel spatial separation. High-K dielectrics have been shown to reduce leakage current with smaller decrease in transconductance in Si-CMOS technology and therefore, applied to GaN technology. ALD is recognized as a novel method for high-κ gate dielectric deposition, where H2O is primarily used as the oxygen source for growth; excellent properties have been reported. However, ozone-grown films show further suppressed leakage current and offer better interfacial quality on silicon. In this study, MOSCaps have been developed on GaN/AlGaN/GaN heterostructures with PECVD Si3N4 and ALD HfO2 as the passivation layer and gate dielectric, respectively. HfO2 was grown using either H2O or ozone as the oxygen source. XPS analysis, capacitance-voltage, conductance-voltage and leakage current-voltage characteristics have been used as probes to study the quality of the film and its interface with the III-N semiconductor. It is observed that due to the sufficient supply of oxygen, ozone helps in the formation of a better bulk dielectric by more complete oxidation. However, the interface is degraded by uncontrolled surface oxidation of the barrier layer or/and penetration of oxygen impurities, creating shallow donor traps aiding in leakage. The overall leakage current with the ozone-grown dielectric is reduced by almost half-an-order of magnitude due to the better bulk dielectric achieved

Through Silicon Via Field-Effect Transistor with Hafnia-based Ferroelectrics and the Doping of Silicon by Gallium Implantation Utilizing a Focused Ion Beam System

3-dimensional integration has become a standard to further increase the transistor density and to enhance the integrated functionality in microchips. Integrated circuits are stacked on top of each other and copper-filled through-silicon VIAs (TSVs) are the industry-accepted choice for their vertical electrical connection. The aim of this work is to functionalize the TSVs by implementing vertical field-effect transistors inside the via holes. The front and back sides of 200 ... 300 µm thin silicon wafers were doped to create the source/drain regions of n- and p-FETs. The TSVFETs showed very stable saturation currents and on/off current ratios of about 10^6 (n-TSVFET) and 10^3 (p-TSVFET) for a gate voltage magnitude of 4V. The use of hafnium zirconium oxide on a thin SiO_2 interface layer as gate dielectric material in a p-TSVFET, enabled the implementation of a charge trapping memory inside the TSVs, showing a memory window of about 1V. This allows the non-volatile storage of the transistor on/off state. In addition, the demonstration of the use of gallium as the source/drain dopant in planar p-FET test structures (ion implanted from a focused ion beam tool) paves the way for maskless doping and for a process flow with a low thermal budget. It was shown, that ion implanted gallium can be activated and annealed at relatively low temperatures of 500 °C ... 700 °C.:Abstract / Kurzzusammenfassung Danksagung Index I List of Figures III List of Tables X List of Symbols XI List of Abbreviations XV 1 Introduction 1 2 Fundamentals 5 2.1 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) 5 2.1.1 Historical Development - Technological Advancements 7 2.1.2 Field-Effect Transistors in Semiconductor Memories 10 2.2 3D Integration and the Use of TSVs (Through Silicon VIAs) 16 2.3 Doping of Silicon 19 2.3.1 Doping by Thermal Diffusion 20 2.3.2 Doping by Ion Implantation 22 3 Electrical Characterization 24 3.1 Resistivity Measurements 24 3.1.1 Resistance Determination by Four-Point Probes Measurement 24 3.1.2 Contact Resistivity 27 3.1.3 Doping Concentration 32 3.2 C-V Measurements 35 3.2.1 Fundamentals of MIS C-V Measurements 35 3.2.2 Interpretation of C-V Measurements 37 3.3 Transistor Measurements 41 3.3.1 Output Characteristics (I_D-V_D) 41 3.3.2 Transfer Characteristics (I_D-V_G) 42 4 TSV Transistor 45 4.1 Idea and Motivation 45 4.2 Design and Layout of the TSV Transistor 47 4.2.1 Design of the TSV Transistor Structures 47 4.2.2 Test Structures for Planar FETs 48 5 Variations in the Integration Scheme of the TSV Transistor 51 5.1 Doping by Diffusion from Thin Films 51 5.1.1 Determination of Doping Profiles 52 5.1.2 n- and p- TSVFETs Doped Manufactures by the Use of the Diffusion Technique 59 5.2 Ferroelectric Hafnium-Zirconium-Oxide (HZO) in the Gate Stack 81 5.2.1 Planar ferroelectric p-MOSFETs Doped by Thermal Diffusion 82 5.2.2 p-TSVFETs with Hafnium-Zirconium-Oxide Metal Gate 90 5.3 Doping by Ion Implantation of Gallium with a Focused Ion Beam (FIB) Tool 96 5.3.1 Ga doped Si Diodes 97 5.3.2 Planar p-MOSFETs Doped by Ga Implantation 108 5.3.3 Proposal for a parallel integration of Cu TSVs and p-TSVFETs 117 6 Summary and Outlook 120 Bibliography XVIII A Appendix XXXVI A.1 Resistivity and Dopant Density XXXVI A.2 Mask set for the TSVFET XXXVII A.3 Mask Design of the Planar Test Structures XXXVIII Curriculum Vitae XXXIX List of Scientific Publications XL

The development of magnetic tunnel junction fabrication techniques

The discovery of large, room temperature magnetoresistance (MR) in magnetic tunnel junctions in 1995 sparked great interest in these devices. Their potential applications include hard disk read head sensors and magnetic random access memory (MRAM). However, the fabrication of repeatable, high quality magnetic tunnel junctions is still problematic. This thesis investigates methods to improve and quantify the quality of tunnel junction fabrication. Superconductor-insulator-superconductor (SIS) and superconductor-insulatorferromagnet (SIF) tunnel junctions were used to develop the fabrication route, due to the ease of identifying their faults. The effect on SIF device quality of interchanging the top and bottom electrodes was monitored. The relationship between the superconducting and normal state characteristics of SIS junctions was investigated. Criteria were formulated to identify devices in which tunneling is not the principal conduction mechanism in normal metal-insulator-normal metal junctions. Magnetic tunnel junctions (MTJs) were produced on the basis of the fabrication route developed with SIS and SIF devices. MTJs in which tunneling is the principal conduction mechanism do not necessarily demonstrate high MR, due to effects such as magnetic coupling between the electrodes and spin scattering. Transmission electron microscope images were used to study magnetic tunnel junction structure, revealing an amorphous barrier and crystalline electrodes. The decoration of pinholes and weak-links by copper electrodeposition was investigated. A new technique is presented to identify the number of copper deposits present in a thin insulating film. The effect of roughness, aluminium thickness and voltage on the number of pinholes and weak-links per unit area was studied. High frequency testing of read heads at wafer level was performed with a network analyser. Design implications for read head geometry were investigated, independent of magnetic performance. This technique has great potential to aid the rapid development of read and write heads whilst improving understanding of the system.EPSRC Seagate Technolog

Study of High-k Dielectrics and their Interfaces on Semiconductors for Device Applications

This thesis has focused on two emerging applications of high-k dielectrics in Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) and in Metal-InsulatorSemiconductor High Electron Mobility Transistors (MIS-HEMTs). The key aim has been to propose the best routes for passivation of semiconductor/high-k oxide interfaces by investigating the band alignments and interface properties of several oxides, such as Tm2O3, Ta2O5, ZrO2, Al2O3 and MgO, deposited on different semiconductors: Si, Ge, GaN, InGaAs and InGaSb. The electrical characterisation of fabricated MIS capacitor and (MIS)-HEMT devices have also been performed. Thulium silicate (TmSiO) has been identified as a promising candidate for integration as interfacial layer (IL) in HfO2/TiN MOSFETs. The physical properties of Tm2O3/IL/Si interface have been elucidated, where IL (TmSiO) has been formed using different post-deposition annealing (PDA) temperatures, from 550 to 750 °C. It has been found that the best-scaled stack (sub-nm IL) is formed at 550 °C PDA with a graded interface layer and a strong SiOx (Si 3+) component. A large valence band offset (VBO) of 2.8 eV and a large conduction band offset (CBO) of 1.9 eV have been derived for Tm2O3/Si by X-ray photoelectron spectroscopy (XPS) and variable angle spectroscopic ellipsometry. Further increase of device performance can be achieved by replacing Si with GaN for high frequency, high power and high-temperature operation. In this thesis, several GaN cleaning procedures have been considered: 30% NH4OH, 20% (NH4)2S, and 37% HCl. It has been found that the HCl treatment shows the lowest oxygen contamination and Garich surface, and hence has been used prior sputtering of Ta2O5, Al2O3, ZrO2 and MgO on GaN. The large VBOs of 1.1 eV and 1.2 eV have been derived for Al2O3 and MgO on GaN respectively, using XPS and Kraut’s method; the corresponding CBOs are 2.0 eV and 2.8 eV respectively, taking into account the band gaps of Al2O3 (6.5 eV) and MgO (7.4 eV) determined from XPS O 1s electron energy spectra. The lowest leakage currents were obtained for devices with Al2O3 and MgO, i.e. 5.3 ×10-6 A/cm2 and 3.2 ×10-6 A/cm2 at 1 V, respectively in agreement with high band offsets (> 1 eV). Furthermore, the effect of different surface treatments (HCl, O2 plasma and 1-Octadecanethiol (ODT)) prior to atomic layer deposition of Al2O3 on the GaN/AlGaN/GaN heterostructure has been investigated. The MIS-HEMTs fabricated using the low-cost ODT GaN surface treatment have been found to exhibit superior performance for power switching applications such as a low threshold voltage, VT of -12.3 V, hysteresis of 0.12 V, a small subthreshold voltage slope (SS) of 73 mV/dec, and a low density of interface states, Dit of 3.0 x10^12 cm-2eV-1. A comprehensive novel study of HfO2/InGaAs and Al2O3/InGaSb interfaces have also been conducted for use in III-V based MOSFETs. The addition of the plasma H2/TMA/H2 pre-cleaning has been found to be very effective in recovering etch damage on InGaAs, especially for (110) orientation, and led to the improvement of electrical characteristics. Furthermore, the combination of H2 plasma exposure and forming gas anneal yielded significantly improved metrics for Al2O3/InGaSb over the control HCltreated sample, with the 150 W plasma treatment giving both the highest capacitance and the lowest stretch out