Hybrid Diagnosis Model To Determine Fault Isolation For Scan Chain Failure Analysis On 22nm Fabrication Process

With the rapid growth of Very Large Scale Integration (VLSI) in complex designs, there is high demand for Design for Testability (DFT). Vast study has proven that Scan based testing is achieving good test coverage with lower cost and smaller die area and is widely used in the industry. Scan chain fault diagnosis plays an important role as with the implementation of Scan based testing, it is reported that 10%-30% of defects in a Scan based design occurs within the Scan chain itself. Currently, there are three main types of stand-alone diagnosis models available, which are: software-based diagnosis, tester-based diagnosis and hardware-based diagnosis, where each has its disadvantages and limitations. In this project, the author proposed a hybrid Scan chain failure analysis technique that uses the proposed software-based diagnosis to obtain a list of possible failing suspect Scan cells, followed by the proposed tester-based diagnosis to further isolate the fault to a single failing device suspect. This proposed hybrid diagnosis algorithm ensures that Scan chain faults such as stuck-at and transition faults can be root-caused with lesser time and low complexity for both solid and marginal failures. Four case studies were successfully carried out to evaluate the proposed hybrid diagnosis algorithm on a 22nm fabrication process technology Device under Test (DUT) System-on-Chip (SOC) product, where the fault isolation was able to isolate a single failing device suspect for all four case studies, indicating a 100% fault isolation success rate

On-Line Dependability Enhancement of Multiprocessor SoCs by Resource Management

This paper describes a new approach towards dependable design of homogeneous multi-processor SoCs in an example satellite-navigation application. First, the NoC dependability is functionally verified via embedded software. Then the Xentium processor tiles are periodically verified via on-line self-testing techniques, by using a new IIP Dependability Manager. Based on the Dependability Manager results, faulty tiles are electronically excluded and replaced by fault-free spare tiles via on-line resource management. This integrated approach enables fast electronic fault detection/diagnosis and repair, and hence a high system availability. The dependability application runs in parallel with the actual application, resulting in a very dependable system. All parts have been verified by simulation

Crypto-test-lab for security validation of ECC co-processor test infrastructure

© 20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting /republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other worksElliptic Curve Cryptography (ECC) is a technology for public-key cryptography that is becoming increasingly popular because it provides greater speed and implementation compactness than other public-key technologies. Calculations, however, may not be executed by software, since it would be so time consuming, thus an ECC co-processor is commonly included to accelerate the speed. Test infrastructure in crypto co-processors is often avoided because it poses serious security holes against adversaries. However, ECC co-processors include complex modules for which only functional test methodologies are unsuitable, because they would take an unacceptably long time during the production test. Therefore, some internal test infrastructure is always included to permit the application of structural test techniques. Designing a secure test infrastructure is quite a complex task that relies on the designer's experience and on trial & error iterations over a series of different types of attacks. Most of the severe attacks cannot be simulated because of the demanding computational effort and the lack of proper attack models. Therefore, prototypes are prepared using FPGAs. In this paper, a Crypto-Test-Lab is presented that includes an ECC co-processor with flexible test infrastructure. Its purpose is to facilitate the design and validation of secure strategies for testing in this type of co-processor.Postprint (author's final draft

The integration of on-line monitoring and reconfiguration functions using IEEE1149.4 into a safety critical automotive electronic control unit.

This paper presents an innovative application of IEEE 1149.4 and the integrated diagnostic reconfiguration (IDR) as tools for the implementation of an embedded test solution for an automotive electronic control unit, implemented as a fully integrated mixed signal system. The paper describes how the test architecture can be used for fault avoidance with results from a hardware prototype presented. The paper concludes that fault avoidance can be integrated into mixed signal electronic systems to handle key failure modes

Using biomarkers to predict TB treatment duration (Predict TB): a prospective, randomized, noninferiority, treatment shortening clinical trial

Background : By the early 1980s, tuberculosis treatment was shortened from 24 to 6 months, maintaining relapse rates of 1-2%. Subsequent trials attempting shorter durations have failed, with 4-month arms consistently having relapse rates of 15-20%. One trial shortened treatment only among those without baseline cavity on chest x-ray and whose month 2 sputum culture converted to negative. The 4-month arm relapse rate decreased to 7% but was still significantly worse than the 6-month arm (1.6%, P<0.01).  We hypothesize that PET/CT characteristics at baseline, PET/CT changes at one month, and markers of residual bacterial load will identify patients with tuberculosis who can be cured with 4 months (16 weeks) of standard treatment.Methods: This is a prospective, multicenter, randomized, phase 2b, noninferiority clinical trial of pulmonary tuberculosis participants. Those eligible start standard of care treatment. PET/CT scans are done at weeks 0, 4, and 16 or 24. Participants who do not meet early treatment completion criteria (baseline radiologic severity, radiologic response at one month, and GeneXpert-detectable bacilli at four months) are placed in Arm A (24 weeks of standard therapy). Those who meet the early treatment completion criteria are randomized at week 16 to continue treatment to week 24 (Arm B) or complete treatment at week 16 (Arm C). The primary endpoint compares the treatment success rate at 18 months between Arms B and C.Discussion: Multiple biomarkers have been assessed to predict TB treatment outcomes. This study uses PET/CT scans and GeneXpert (Xpert) cycle threshold to risk stratify participants. PET/CT scans are not applicable to global public health but could be used in clinical trials to stratify participants and possibly become a surrogate endpoint. If the Predict TB trial is successful, other immunological biomarkers or transcriptional signatures that correlate with treatment outcome may be identified. TRIAL REGISTRATION: NCT02821832

A novel scan segmentation design method for avoiding shift timing failure in scan testing

ITC : 2011 IEEE International Test Conference , 20-22 Sep. 2011 , Anaheim, CA, USAHigh power consumption in scan testing can cause undue yield loss which has increasingly become a serious problem for deep-submicron VLSI circuits. Growing evidence attributes this problem to shift timing failures, which are primarily caused by excessive switching activity in the proximities of clock paths that tends to introduce severe clock skew due to IR-drop-induced delay increase. This paper is the first of its kind to address this critical issue with a novel layout-aware scheme based on scan segmentation design, called LCTI-SS (Low-Clock-Tree-Impact Scan Segmentation). An optimal combination of scan segments is identified for simultaneous clocking so that the switching activity in the proximities of clock trees is reduced while maintaining the average power reduction effect on conventional scan segmentation. Experimental results on benchmark and industrial circuits have demonstrated the advantage of the LCTI-SS scheme

Longitudinal study on low-dose aspirin versus placebo administration in silent brain infarcts: the silence study

Background. We investigated low-dose aspirin (ASA) efficacy and safety in subjects with silent brain infarcts (SBIs) in preventing new cerebrovascular (CVD) events as well as cognitive impairment. Methods. We included subjects aged ≥45 years, with at least one SBI and no previous CVD. Subjects were followed up to 4 years assessing CVD and SBI incidence as primary endpoint and as secondary endpoints: (a) cardiovascular and adverse events and (b) cognitive impairment. Results. Thirty-six subjects received ASA while 47 were untreated. Primary endpoint occurred in 9 controls (19.1%) versus 2 (5.6%) in the ASA group (p=0.10). Secondary endpoints did not differ in the two groups. Only baseline leukoaraiosis predicts primary [OR 5.4 (95%CI 1.3-22.9, p=0.022)] and secondary endpoint-A [3.2 (95%CI 1.1-9.6, p=0.040)] occurrence. Conclusions. These data show an increase of new CVD events in the untreated group. Despite the study limitations, SBI seems to be a negative prognostic factor and ASA preventive treatment might improve SBI prognosis. EU Clinical trial is registered with EudraCT Number: 2005-000996-16; Sponsor Protocol Number: 694/30.06.04

Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects

We present a combined hardware-software based approach to scan-chain diagnosis, when the outcome of a test may be affected by system faults occurring in the logic outside of the scan chain. For the hardware component we adopt the double-tree scan (DTS) chain architecture, which has previously been shown to be effective in reducing power, volume, and application time of tests for stuck-at and delay faults. We develop a version of flush test which can resolve a multiple fault in a DTS chain to a small number of suspect candidates. Further resolution to a unique multiple fault is enabled by the software component comprising of fault simulation and analysis of the response of the circuit to test patterns produced by ATPG. Experimental results on benchmark circuits show that near-perfect scan-chain diagnosis for multiple faults is possible even when a large number of random system faults are injected in the circuit