An Electromigration and Thermal Model of Power Wires for a Priori High-Level Reliability Prediction

In this paper, a simple power-distribution electrothermal model including the interconnect self-heating is used together with a statistical model of average and rms currents of functional blocks and a high-level model of fanout distribution and interconnect wirelength. Following the 2001 SIA roadmap projections, we are able to predict a priori that the minimum width that satisfies the electromigration constraints does not scale like the minimum metal pitch in future technology nodes. As a consequence, the percentage of chip area covered by power lines is expected to increase at the expense of wiring resources unless proper countermeasures are taken. Some possible solutions are proposed in the paper

A novel intermittent fault detection algorithm and health monitoring for electronic interconnections

There are various occurrences and root causes that result in no-fault-found (NFF) events but an intermittent fault (IF) is the most frustrating. This paper describes the challenging and most important area of an IF detection and health monitoring that focuses toward NFF situation in electronics interconnections. The experimental work focuses on mechanically-induced intermittent conditions in connectors. This paper illustrates a test regime, which can be used to repeatedly reproduce intermittence in electronic connectors, while subjected to vibration. A novel algorithm is used to detect an IF in interconnection. It sends a sine wave and decodes the received signal for intermittent information from the channel. This algorithm has been simulated to capture an IF signature using PSpice (electronic circuit simulation software). A simulated circuit is implemented for practical verification. However, measurements are presented using an oscilloscope. The results of this experiment provide an insight into the limitations of existing test equipment and requirements for future IF detection techniques. Aside from scheduled maintenance, this paper considers the possibility for in-service intermittent detection to be built into future systems, i.e., can IFs be captured without external test gear

Interconnect yield analysis and fault tolerance for field programmable gate arrays

Imperial Users onl

Testing Layered Interconnection Networks

We present an approach for fault detection in layered interconnection networks (LINs). An LIN is a generalized multistage interconnection network commonly used in reconfigurable systems; the nets (links) are arranged in sets (referred to as layers) of different size. Switching elements (made of simple switches such as transmission-gate-like devices) are arranged in a cascade to connect pairs of layers. The switching elements of an LIN have the same number of switches, but the switching patterns may not be uniform. A comprehensive fault model for the nets and switches is assumed at physical and behavioral levels. Testing requires configuring the LIN multiple times. Using a graph approach, it is proven that the minimal set of configurations corresponds to the node disjoint path sets. The proposed approach is based on two novel results in the execution of the network flow algorithm to find node disjoint path sets, while retaining optimality in the number of configurations. These objectives are accomplished by finding a feasible flow such that the maximal degree can be iteratively decreased, while guaranteeing the existence of an appropriate circulation. Net adjacencies are also tested for possible bridge faults (shorts). To account for 100 percent fault coverage of bridge faults a postprocessing algorithm may be required; bounds on its complexity are provided. The execution complexity of the proposed approach (inclusive of test vector generation and post-processing) is O(N4WL), where N is the total number of nets, W is the number of switches per switching element, and L is the number of layers. Extensive simulation results are provided

Learning Graph Patterns of Reflection Coefficient for Non-destructive Diagnosis of Cu Interconnects

With the increasing operating frequencies and clock speeds in processors, interconnects affect both the reliability and performance of entire electronic systems. Fault detection and diagnosis of the interconnects are crucial for prognostics and health management (PHM) of electronics. However, traditional approaches using electrical signals as prognostic factors often face challenges in distinguishing defect root causes, necessitating additional destructive evaluations, and are prone to noise interference, leading to potential false alarms. To address these limitations, this paper introduces a novel approach for non-destructive detection and diagnosis of defects in Cu interconnects, offering early detection, enhanced diagnostic accuracy, and noise resilience. Our approach uniquely analyzes both the root cause and severity of interconnect defects by leveraging graph patterns of reflection coefficient, a technique distinct from traditional time series signal analysis. We experimentally demonstrate that the graph patterns possess the capability for fault diagnosis and serve as effective input data for learning algorithms. Additionally, we introduce a novel severity rating ensemble learning (SREL) approach, which significantly enhances diagnostic accuracy and noise robustness. Experimental results demonstrate that the proposed method outperforms conventional machine learning methods and multi-class convolutional neural networks (CNN), achieving a maximum accuracy of 99.3%, especially under elevated noise levels

Intermittent fault diagnosis and health monitoring for electronic interconnects

Literature survey and correspondence with industrial sector shows that No-Fault-Found (NFF) is a major concern in through life engineering services, especially for defence, aerospace, and other transport industry. There are various occurrences and root causes that result in NFF events but intermittent interconnections are the most frustrating. This is because it disappears while testing, and missed out by diagnostic equipment. This thesis describes the challenging and most important area of intermittent fault detection and health monitoring that focuses towards NFF situation in electronics interconnections. After introduction, this thesis starts with literature survey and describes financial impact on aerospace and other transport industry. It highlights NFF technologies and discuss different facts and their impact on NFF. Then It goes into experimental study that how repeatedly intermittent fault could be replicated. It describes a novel fault replicator that can generate repeatedly IFs for further experimental study on diagnosis techniques/algorithms. The novel IF replicator provide for single and multipoint intermittent connection. The experimental work focuses on mechanically induced intermittent conditions in connectors. This work illustrates a test regime that can be used to repeatedly reproduce intermittency in electronic connectors whilst subjected to vibration ... [cont.]

Study on Intermittent Faults and Electrical Continuity

connector, or incorrect installation during initial manufacture and assembly. Unless such issues are narrowed down to a specific root cause, any corrective actions or troubleshooting will be difficult to carry out, and hence its resolution may not make its way into future designs of the system. This leads to further susceptibility to NFF. Intermittent behaviour is often a clear sign of a partially damaged connector, or a connector undergoing a particular degradation mechanism, with the level of intermittency being further aggravated through process variation of harsh environments and parametric faults. In order to further our understanding of the relationship between degradation, operating conditions, intermittent behaviour within the subject, an experimental investigations have been carried out. This paper is a work in progress paper that illustrates a test regime that has been used to stimulate intermittence in electronic connectors whilst subjected to vibration, using both a traditional oscilloscope and bespoke intermittent fault detection equipment, in order to capture an intermittent signature. The results of these experiments provide an insight into the limitations of test equipment and requirements for future intermittent fault detection techniques

Implementation of Static and Semi-Static Versions of a 24+8x8 Quad-rail NULL Convention Multiply and Accumulate Unit

This paper focuses on implementing a 2s complement 8x8 dual-rail bit-wise pipelined multiplier using the asynchronous null convention logic (NCL) paradigm. The design utilizes a Wallace tree for partial product summation, and is implemented and simulated in VHDL, the transistor level, and the physical level, using a 1.8V 0.18mum TSMC CMOS process. The multiplier is realized using both static and semi-static versions of the NCL gates; and these two implementations are compared in terms of area, power, and speed

A Framework for the Detection of Crosstalk Noise in FPGAs

In recent years, crosstalk noise has emerged a serious problem because more and more devices and wires have been packed on electronic chips. As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk noise is the important phenomenon that must be taken into account. Despite of being more immune to crosstalk noise than their ASIC (application specific integrated circuit) counterparts, the dense interconnected structures of FPGAs (field programmable gate arrays) invite more vulnerabilities with crosstalk noise. Due to the lack of electrical detail concerning FPGA devices it is quite difficult to test the faults affected by crosstalk noise. This paper proposes a new approach for detecting the effects such as glitches and delays in transition that are due to crosstalk noise in FPGAs. This approach is similar to the BIST (built-in self test) technique in that it incorporates the test pattern generator to generate the test vectors and the analyzer to analyze the crosstalk faults without any overhead for testing