Construction of an Expert System Based on Fuzzy Logic for Diagnosis of Analog Electronic Circuits

The paper presents construction of the fuzzy logic system to analog circuits soft fault diagnosis. The classical dictionary construction is replaced by fuzzy rule system. The first part refers to analog fault diagnosis, its techniques, approaches and goals. It clarifies common strategy and define differences between detecting, locating and identifying a fault in analog electronic circuit. The second part is focused on a creation of fuzzy rule expert system with use of sensitivity functions and known circuit topology. To detect, locate and identify a faulty element in a circuit the sensitivity matrix is used. The advantage of the method is its utilization in all, AC, DC and time domain. The fuzzy system, like the classical fault dictionary, can detect and locate single catastrophic faults and, on the contrary to the classical one, it also detects and locates parametric faults. Moreover, it allows identification of these faults, such that sign of the faulty parameter deviation is designated. The method has deterministic character as well as  it can be applied on the verification and production stage

A MLMVN WITH ARBITRARY COMPLEX-VALUED INPUTS AND A HYBRID TESTABILITY APPROACH FOR THE EXTRACTION OF LUMPED MODELS USING FRA

A procedure for the identification of lumped models of distributed parameter electromagnetic systems is presented in this paper. A Frequency Response Analysis (FRA) of the device to be modeled is performed, executing repeated measurements or intensive simulations. The method can be used to extract the values of the components. The fundamental brick of this architecture is a multi-valued neuron (MVN), used in a multilayer neural network (MLMVN); the neuron is modified in order to use arbitrary complex-valued inputs, which represent the frequency response of the device. It is shown that this modification requires just a slight change in the MLMVN learning algorithm. The method is tested over three completely different examples to clearly explain its generality

Symbolic tolerance and sensitivity analysis of large scale electronic circuits

Available from British Library Document Supply Centre-DSC:DXN029693 / BLDSC - British Library Document Supply CentreSIGLEGBUnited Kingdo

Quiescent current testing of CMOS data converters

Power supply quiescent current (IDDQ) testing has been very effective in VLSI circuits designed in CMOS processes detecting physical defects such as open and shorts and bridging defects. However, in sub-micron VLSI circuits, IDDQ is masked by the increased subthreshold (leakage) current of MOSFETs affecting the efficiency of I¬DDQ testing. In this work, an attempt has been made to perform robust IDDQ testing in presence of increased leakage current by suitably modifying some of the test methods normally used in industry. Digital CMOS integrated circuits have been tested successfully using IDDQ and IDDQ methods for physical defects. However, testing of analog circuits is still a problem due to variation in design from one specific application to other. The increased leakage current further complicates not only the design but also testing. Mixed-signal integrated circuits such as the data converters are even more difficult to test because both analog and digital functions are built on the same substrate. We have re-examined both IDDQ and IDDQ methods of testing digital CMOS VLSI circuits and added features to minimize the influence of leakage current. We have designed built-in current sensors (BICS) for on-chip testing of analog and mixed-signal integrated circuits. We have also combined quiescent current testing with oscillation and transient current test techniques to map large number of manufacturing defects on a chip. In testing, we have used a simple method of injecting faults simulating manufacturing defects invented in our VLSI research group. We present design and testing of analog and mixed-signal integrated circuits with on-chip BICS such as an operational amplifier, 12-bit charge scaling architecture based digital-to-analog converter (DAC), 12-bit recycling architecture based analog-to-digital converter (ADC) and operational amplifier with floating gate inputs. The designed circuits are fabricated in 0.5 μm and 1.5 μm n-well CMOS processes and tested. Experimentally observed results of the fabricated devices are compared with simulations from SPICE using MOS level 3 and BSIM3.1 model parameters for 1.5 μm and 0.5 μm n-well CMOS technologies, respectively. We have also explored the possibility of using noise in VLSI circuits for testing defects and present the method we have developed