3 research outputs found
Architecture to System Level Analysis of DMTJ-based Cache Memory
The present work details the construction of a simulation framework from architecture to system level by considering a 0.8V FinFET technology and the single- and double-barrier magnetic tunnel junction (MTJ)...El presente trabajo detalla la construcción de una plantilla de simulación desde el nivel de arquitectura hasta el nivel de sistema considerando una tecnologÃa FinFET de 0.8V con unión de túnel magnético de barrera simple y doble (MTJ)..
Valley-Spin Hall Effect-based Nonvolatile Memory with Exchange-Coupling-Enabled Electrical Isolation of Read and Write Paths
Valley-spin hall (VSH) effect in monolayer WSe2 has been shown to exhibit
highly beneficial features for nonvolatile memory (NVM) design. Key advantages
of VSH-based magnetic random-access memory (VSH-MRAM) over spin orbit torque
(SOT)-MRAM include access transistor-less compact bit-cell and low power
switching of perpendicular magnetic anisotropy (PMA) magnets. Nevertheless,
large device resistance in the read path (RS) due to low mobility of WSe2 and
Schottky contacts deteriorates sense margin, offsetting the benefits of
VSH-MRAM. To address this limitation, we propose another flavor of VSH-based
MRAM that (while inheriting most of the benefits of VSH-MRAM) achieves lower RS
in the read path by electrically isolating the read and write terminals. This
is enabled by coupling VSH with electrically-isolated but magnetically-coupled
PMA magnets via interlayer exchange-coupling. Designing the proposed devices
using object oriented micro magnetic framework (OOMMF) simulation, we ensure
the robustness of the exchange-coupled PMA system under process variations. To
maintain a compact memory footprint, we share the read access transistor across
multiple bit-cells. Compared to the existing VSH-MRAMs, our design achieves
39%-42% and 36%-46% reduction in read time and energy, respectively, along with
1.1X-1.3X larger sense margin at a comparable area. This comes at the cost of
1.7X and 2.0X increase in write time and energy, respectively. Thus, the
proposed design is suitable for applications in which reads are more dominant
than writes
Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing
Smart material implication (SIMPLY) logic has been recently proposed for the design of energy-efficient Logic-in-Memory (LIM) architectures based on non-volatile resistive memory devices. The SIMPLY logic is enabled by adding a comparator to the conventional IMPLY scheme. This allows performing a preliminary READ operation and hence the SET operation only in the case it is actually required. This work explores the SIMPLY logic scheme using nanoscale spin-transfer torque magnetic tunnel junction (STT-MTJ) devices. The performance of the STT-MTJ based SIMPLY architecture is analyzed by varying the load resistor and applied voltages to implement both READ and SET operations, while also investigating the effect of temperature on circuit operation. Obtained results show an existing tradeoff between error rate and energy consumption, which can be effectively managed by properly setting the values of load resistor and applied voltages. In addition, our analysis proves that tracking the temperature dependence of the MTJ properties through a proportional to absolute temperature (PTAT) reference voltage at the input of the comparator is beneficial to mitigate the reliability degradation under temperature variations