Heterogeneous Integration of RF and Microwave Systems Using Multi-layer Low-Temperature Co-fired Ceramics Technology

[eng] The aim of this work is the development of a modelling methodology for the fast analysis of non-radiative multilayer RF passive components without compromising solution accuracy. Instead of following a compact model approach, oftenly used in integrated technologies, the method is based on a specialized quasi-static partial element equivalent circuit (PEEC) numerical solver. Besides speed and accuracy, the solver can be embedded in circuit simulators; thus, models are already available in the schematic entry. Using this framework, model scalability is enhanced in terms of geometry, substrate cross-section, material properties, topology and boundary conditions. The dissertation starts showing the actual performance of the obtained solver and the motivations beneath its development. Then, the description about solver development is splitted in three parts, but all of them are interrelated. First, the PEEC formulation is adapted according to relevant electromagnetic behaviour of the component. It is worth stressing that a different perspective related to the principle of virtual work is used in this formulation. The second part deals with the evaluation of partial elements, the core of the solver. It is carried out using analytical space-domain close-form solutions of the Green’s function (GF) of the substrate. Partial elements are then assembled into a mesh. Therefore, the importance of the mesh up on solution accuracy is discussed in the last part and a basic layout aware mesh generator is proposed. Practical application of the methodology includes the implementation of a library of RF passives for multilayer substrate. For validation, the chosen substrate is a low temperature co-fired ceramics (LTCC) technology. Different set of devices have been fabricated, characterized and compared against model prediction. In addition, the obtained results are also verified using state-of-the-art electromagnetic solvers.[spa] El objetivo de este trabajo es el desarrollo de una metodología de modelado para el análisis rápido, pero sin comprometer la precisión de la solución, de componentes pasivos no radiativos de RF en substratos multicapa. El método se basa en el algoritmo numérico cuasi-estático de los elementos parciales de circuito equivalente (PEEC). Éste puede ser incorporado en simuladores de circuitos; por tanto, los modelos ya están disponibles en la entrada de esquemático de forma transparente para el diseñador de circuitos. Utilizando este marco, la escalabilidad del modelo se mejora en términos de la geometría, la definición del corte tecnológico, las propiedades del material, la topología del componente y las condiciones de contorno electro-magnéticas. Esta disertación comienza mostrando las motivaciones que han llevado a su desarrollo y la capacidad real del método de resolución obtenido. A partir de aquí, se realiza la descripción de todo el desarrollo del marco numérico que se divide en tres partes que están interrelacionadas. En primer lugar, la formulación PEEC se adapta según el comportamiento electromagnético real del componente. Vale la pena subrayar que en esta formulación se utiliza una perspectiva diferente a la habitual y que está relacionada con el principio de los trabajos virtuales de d’Alembert. La segunda parte trata de cómo se evalúan los elementos parciales y constituye el núcleo principal del algoritmo. Se lleva a cabo utilizando soluciones analíticas de la función de Green (GF) del sustrato en el dominio espacial. Los elementos parciales, que forman la malla numérica del modelo, se ensamblan en la matriz del sistema siguiendo un procedimiento de análisis nodal modificado (MNA). En la última parte, se discute la importancia de la malla sobre la precisión de la solución y se propone un generador de malla basado en la física del componente y no sólo en la descripción de la geometría. Como aplicación práctica de la metodología, se realiza la generación de una biblioteca de componentes pasivos RF para sustratos multicapa

A thermal simulation process based on electrical modeling for complex interconnect, packaging, and 3DI structures

To reduce the product development time and achieve first-pass silicon success, fast and accurate estimation of very-large-scale integration (VLSI) interconnect, packaging and 3DI (3D integrated circuits) thermal profiles has become important. Present commercial thermal analysis tools are incapable of handling very complex structures and have integration difficulties with existing design flows. Many analytical thermal models, which could provide fast estimates, are either too specific or oversimplified. This paper highlights a methodology, which exploits electrical resistance solvers for thermal simulation, to allow acquisition of thermal profiles of complex structures with good accuracy and reasonable computation cost. Moreover, a novel accurate closed-form thermal model is developed. The model allows an isotropic or anisotropic equivalent medium to replace the noncritical back-end-of-line (BEOL) regions so that the simulation complexity is dramatically reduced. Using these techniques, this paper introduces the thermal modeling of practical complex VLSI structures to facilitate thermal guideline generation. It also demonstrates the benefits of the proposed anisotropic equivalent medium approximation for real VLSI structures in terms of the accuracy and computational cost. © 2006 IEEE.published_or_final_versio

FINITE ELEMENT AND IMAGING APPROACHES TO ANALYZE MULTISCALE ELECTROTHERMAL PHENOMENA

Electrothermal effects are crucial in the design and optimization of electronic devices. Thermoreflectance (TR) imaging enables transient thermal characterization at submicron to centimeter scales. Typically, finite element methods (FEM) are used to calculate the temperature profile in devices and ICs with complex geometry. By comparing theory and experiment, important material parameters and device characteristics are extracted. In this work we combine TR and FEM with image blurring/reconstruction techniques to improve electrothermal characterization of micron and nanoscale devices

Multiphysics modeling and simulation for large-scale integrated circuits

This dissertation is a process of seeking solutions to two important and challenging problems related to the design of modern integrated circuits (ICs): the ever increasing couplings among the multiphysics and the large problem size arising from the escalating complexity of the designs. A multiphysics-based computer-aided design methodology is proposed and realized to address multiple aspects of a design simultaneously, which include electromagnetics, heat transfer, fluid dynamics, and structure mechanics. The multiphysics simulation is based on the finite element method for its unmatched capabilities in handling complicate geometries and material properties. The capability of the multiphysics simulation is demonstrated through its applications in a variety of important problems, including the static and dynamic IR-drop analyses of power distribution networks, the thermal-ware high-frequency characterization of through-silicon-via structures, the full-wave electromagnetic analysis of high-power RF/microwave circuits, the modeling and analysis of three-dimensional ICs with integrated microchannel cooling, the characterization of micro- and nanoscale electrical-mechanical systems, and the modeling of decoupling capacitor derating in the power integrity simulations. To perform the large-scale analysis in a highly efficient manner, a domain decomposition scheme, parallel computing, and an adaptive time-stepping scheme are incorporated into the proposed multiphysics simulation. Significant reduction in computation time is achieved through the two numerical schemes and the parallel computing with multiple processors

High Speed Test Interface Module Using MEMS Technology

With the transient frequency of available CMOS technologies exceeding hundreds of gigahertz and the increasing complexity of Integrated Circuit (IC) designs, it is now apparent that the architecture of current testers needs to be greatly improved to keep up with the formidable challenges ahead. Test requirements for modern integrated circuits are becoming more stringent, complex and costly. These requirements include an increasing number of test channels, higher test-speeds and enhanced measurement accuracy and resolution. In a conventional test configuration, the signal path from Automatic Test Equipment (ATE) to the Device-Under-Test (DUT) includes long traces of wires. At frequencies above a few gigahertz, testing integrated circuits becomes a challenging task. The effects on transmission lines become critical requiring impedance matching to minimize signal reflection. AC resistance due to the skin effect and electromagnetic coupling caused by radiation can also become important factors affecting the test results. In the design of a Device Interface Board (DIB), the greater the physical separation of the DUT and the ATE pin electronics, the greater the distortion and signal degradation. In this work, a new Test Interface Module (TIM) based on MEMS technology is proposed to reduce the distance between the tester and device-under-test by orders of magnitude. The proposed solution increases the bandwidth of test channels and reduces the undesired effects of transmission lines on the test results. The MEMS test interface includes a fixed socket and a removable socket. The removable socket incorporates MEMS contact springs to provide temporary with the DUT pads and the fixed socket contains a bed of micro-pins to establish electrical connections with the ATE pin electronics. The MEMS based contact springs have been modified to implement a high-density wafer level test probes for Through Silicon Vias (TSVs) in three dimensional integrated circuits (3D-IC). Prototypes have been fabricated using Silicon On Insulator SOI wafer. Experimental results indicate that the proposed architectures can operate up to 50 GHz without much loss or distortion. The MEMS probes can also maintain a good elastic performance without any damage or deformation in the test phase

Constraint-Aware, Scalable, and Efficient Algorithms for Multi-Chip Power Module Layout Optimization

Moving towards an electrified world requires ultra high-density power converters. Electric vehicles, electrified aerospace, data centers, etc. are just a few fields among wide application areas of power electronic systems, where high-density power converters are essential. As a critical part of these power converters, power semiconductor modules and their layout optimization has been identified as a crucial step in achieving the maximum performance and density for wide bandgap technologies (i.e., GaN and SiC). New packaging technologies are also introduced to produce reliable and efficient multichip power module (MCPM) designs to push the current limits. The complexity of the emerging MCPM layouts is surpassing the capability of a manual, iterative design process to produce an optimum design with agile development requirements. An electronic design automation tool called PowerSynth has been introduced with ongoing research toward enhanced capabilities to speed up the optimized MCPM layout design process. This dissertation presents the PowerSynth progression timeline with the methodology updates and corresponding critical results compared to v1.1. The first released version (v1.1) of PowerSynth demonstrated the benefits of layout abstraction, and reduced-order modeling techniques to perform rapid optimization of the MCPM module compared to the traditional, manual, and iterative design approach. However, that version is limited by several key factors: layout representation technique, layout generation algorithms, iterative design-rule-checking (DRC), optimization algorithm candidates, etc. To address these limitations, and enhance PowerSynth’s capabilities, constraint-aware, scalable, and efficient algorithms have been developed and implemented. PowerSynth layout engine has evolved from v1.3 to v2.0 throughout the last five years to incorporate the algorithm updates and generate all 2D/2.5D/3D Manhattan layout solutions. These fundamental changes in the layout generation methodology have also called for updates in the performance modeling techniques and enabled exploring different optimization algorithms. The latest PowerSynth 2 architecture has been implemented to enable electro-thermo-mechanical and reliability optimization on 2D/2.5D/3D MCPM layouts, and set up a path toward cabinet-level optimization. PowerSynth v2.0 computer-aided design (CAD) flow has been hardware-validated through manufacturing and testing of an optimized novel 3D MCPM layout. The flow has shown significant speedup compared to the manual design flow with a comparable optimization result

Enabling Technologies for 3D ICs: TSV Modeling and Analysis

Through silicon via (TSV) based three-dimensional (3D) integrated circuit (IC) aims to stack and interconnect dies or wafers vertically. This emerging technology offers a promising near-term solution for further miniaturization and the performance improvement of electronic systems and follows a more than Moore strategy. Along with the need for low-cost and high-yield process technology, the successful application of TSV technology requires further optimization of the TSV electrical modeling and design. In the millimeter wave (mmW) frequency range, the root mean square (rms) height of the TSV sidewall roughness is comparable to the skin depth and hence becomes a critical factor for TSV modeling and analysis. The impact of TSV sidewall roughness on electrical performance, such as the loss and impedance alteration in the mmW frequency range, is examined and analyzed following the second order small perturbation method. Then, an accurate and efficient electrical model for TSVs has been proposed considering the TSV sidewall roughness effect, the skin effect, and the metal oxide semiconductor (MOS) effect. However, the emerging application of 3D integration involves an advanced bio-inspired computing system which is currently experiencing an explosion of interest. In neuromorphic computing, the high density membrane capacitor plays a key role in the synaptic signaling process, especially in a spike firing analog implementation of neurons. We proposed a novel 3D neuromorphic design architecture in which the redundant and dummy TSVs are reconfigured as membrane capacitors. This modification has been achieved by taking advantage of the metal insulator semiconductor (MIS) structure along the sidewall, strategically engineering the fixed oxide charges in depletion region surrounding the TSVs, and the addition of oxide layer around the bump without changing any process technology. Without increasing the circuit area, these reconfiguration of TSVs can result in substantial power consumption reduction and a significant boost to chip performance and efficiency. Also, depending on the availability of the TSVs, we proposed a novel CAD framework for TSV assignments based on the force-directed optimization and linear perturbation

Integrated through-silicon-via-based inductor design in buck converter for improved efficiency

Introduction. Through-silicon-via (TSV) is one of the most important components of 3D integrated circuits. Similar to two-dimensional circuits, the performance evaluation of 3D circuits depends on both the quality factor and inductance. Therefore, accurate TSV-inductor modeling is required for the design and analysis of 3D integrated circuits. Aim. This work proposes the equivalent circuit model of the TSV-inductor to derive the relations that determine both the quality factor and the inductance by Y-parameters. Methods. The model developed was simulated using MATLAB software, and it was used to evaluate the effect of redistribution lines width, TSV radius, and the number of turns on inductance and quality factor. Additionally, a comparative study was presented between TSV-based inductors and conventional inductors (i.e., spiral and racetrack inductors). Results. These studies show that replacing conventional inductors with TSV-inductors improved the quality factor by 64 % compared to a spiral inductor and 60 % compared to a racetrack inductor. Furthermore, the area of the TSV-inductor was reduced up to 1.2 mm². Using a PSIM simulator, the application of an integrated TSV-inductor in a buck converter was studied, and the simulation gave very good results in 3D integration compared to 2D integration. Moreover, the simulation results demonstrated that using a TSV-inductor in a buck converter could increase its efficiency by up to 15 % and 6 % compared to spiral and racetrack inductors, respectively.Вступ. Наскрізне з’єднання кремнію (TSV) є одним з найважливіших компонентів тривимірних інтегральних схем. Подібно до двовимірних схем, оцінка продуктивності тривимірних схем залежить як від добротності, так і від індуктивності. Тому для проєктування та аналізу тривимірних інтегральних схем необхідне точне моделювання TSV-індуктора. Мета. У цій роботі пропонується еквівалентна модель схеми TSV-індуктора для виведення співвідношень, що визначають як добротність, так і індуктивність за Y-параметрами. Методи. Розроблена модель була змодельована з використанням програмного забезпечення MATLAB та використана для оцінки впливу ширини ліній перерозподілу, радіусу TSV та кількості витків на індуктивність та добротність. Крім того, було представлено порівняльне дослідження між індукторами на основі TSV та звичайними індукторами (тобто спіральними та індукторами типу бігова доріжка). Результати. Ці дослідження показують, що заміна звичайних індукторів на TSV-індуктори покращила добротність на 64 % порівняно зі спіральним індуктором і на 60 % порівняно з індуктором типу бігова доріжка. Крім того, площа TSV-індуктора була зменшена до 1,2 мм². За допомогою симулятора PSIM було вивчено застосування вбудованого дроселя TSV в знижувальному перетворювачі, і моделювання дало дуже хороші результати при 3D-інтеграції порівняно з 2D-інтеграцією. Більш того, результати моделювання показали, що використання TSV-індуктора в понижувальному перетворювачі дозволяє підвищити його ефективність до 15% та 6 % порівняно зі спіральними індукторами та індукторами типу бігова доріжка відповідно

Macro-model of through silicon vias (tsvs) arrays

As continued scaling down of transistors becomes increasingly difficult due to physical and technical issues like the increase of leakage power and total power consumption, overall, 3D integration is now considered a viable solution to get a higher bandwidth and power efficiency. Use of Through-silicon-vias (TSVs), which connects stacked structures die-to-die, is expected to be one of the most important techniques enabling 3D integration. As the number of through silicon Vias (TSVs) exists in the same chip is increasing, an algorithm to build a macro-model is needed to find inter-relationship between TSVs. There are different coupling parameters that exist between TSVs like: capacitive, inductive and resistive coupling. This work provides an algorithm to build a macro-model of an array of TSVs where only capacitive coupling is considered, as it is expected to be the dominating parameter.Using a simulation based technique, where characterization for bundles of TSVs were done and a scaling equation that can give the variationsoccur to capacitance value with scaling the physical dimensions of the TSV (pitch, radius, length and dielectric thickness (tox)) is proposed. The considered ranges for the physical parameters are: radius (from 1um to 10um), tox (from 0.1um to 0.5 um), length (from 10um to 100um) and pitch (from 10um to 95um). Using theproposed algorithm, a macro model can be built in a negligible time, which provides lots of time saving compared to hours required by other tools such as EM simulators or device simulators. The average error range 3% to 6%and a maximum cumulative error of algorithm and usage of scaling equation is 18.2% that occurs at very few dimensions and in very few capacitances from the extracted capacitance values, for both self and coupling capacitance