Modeling of CMOS devices and circuits on flexible ultrathin chips

The field of flexible electronics is rapidly evolving. The ultrathin chips are being used to address the high-performance requirements of many applications. However, simulation and prediction of changes in response of device/circuit due to bending induced stress remains a challenge as of lack of suitable compact models. This makes circuit designing for bendable electronics a difficult task. This paper presents advances in this direction, through compressive and tensile stress studies on transistors and simple circuits such as inverters with different channel lengths and orientations of transistors on ultrathin chips. Different designs of devices and circuits in a standard CMOS 0.18-μm technology were fabricated in two separated chips. The two fabricated chips were thinned down to 20 μm using standard dicing-before-grinding technique steps followed by post-CMOS processing to obtain sufficient bendability (20-mm bending radius, or 0.05% nominal strain). Electrical characterization was performed by packaging the thinned chip on a flexible substrate. Experimental results show change of carrier mobilities in respective transistors, and switching threshold voltage of the inverters during different bending conditions (maximum percentage change of 2% for compressive and 4% for tensile stress). To simulate these changes, a compact model, which is a combination of mathematical equations and extracted parameters from BSIM4, has been developed in Verilog-A and compiled into Cadence Virtuoso environment. The proposed model predicts the mobility variations and threshold voltage in compressive and tensile bending stress conditions and orientations, and shows an agreement with the experimental measurements (1% for compressive and 0.6% for tensile stress mismatch)

Device modelling for bendable piezoelectric FET-based touch sensing system

Flexible electronics is rapidly evolving towards devices and circuits to enable numerous new applications. The high-performance, in terms of response speed, uniformity and reliability, remains a sticking point. The potential solutions for high-performance related challenges bring us back to the timetested silicon based electronics. However, the changes in the response of silicon based devices due to bending related stresses is a concern, especially because there are no suitable models to predict this behavior. This also makes the circuit design a difficult task. This paper reports advances in this direction, through our research on bendable Piezoelectric Oxide Semiconductor Field Effect Transistor (POSFET) based touch sensors. The analytical model of POSFET, complimented with Verilog-A model, is presented to describe the device behavior under normal force in planar and stressed conditions. Further, dynamic readout circuit compensation of POSFET devices have been analyzed and compared with similar arrangement to reduce the piezoresistive effect under tensile and compressive stresses. This approach introduces a first step towards the systematic modeling of stress induced changes in device response. This systematic study will help realize high-performance bendable microsystems with integrated sensors and readout circuitry on ultra-thin chips (UTCs) needed in various applications, in particular, the electronic skin (e-skin)

Device Modelling of Silicon Based High-Performance Flexible Electronics

The area of flexible electronics is rapidly expanding and evolving. With applications requiring high speed and performance, ultra-thin silicon-based electronics has shown its prominence. However, the change in device response upon bending is a major concern. In absence of suitable analytical and design tool friendly model, the behavior under bent condition is hard to predict. This poses challenges to circuit designer working in the bendable electronics field, in laying out a design that can give a precise response in a stressed condition. This paper presents advances in this direction and investigates the effect of compressive and tensile stress on the performance of NMOS and PMOS transistor and a touch sensor comprising a transistor and piezoelectric capacitor

Ultra-thin and flexible CMOS technology: ISFET-based microsystem for biomedical applications

A new paradigm of silicon technology is the ultra-thin chip (UTC) technology and the emerging applications. Very thin integrated circuits (ICs) with through-silicon vias (TSVs) will allow the stacking and interconnection of multiple dies in a compact format allowing a migration towards three-dimensional ICs (3D-ICs). Also, extremely thin and therefore mechanically bendable silicon chips in conjunction with the emerging thin-film and organic semiconductor technologies will enhance the performance and functionality of large-area flexible electronic systems. However, UTC technology requires special attention related to the circuit design, fabrication, dicing and handling of ultra-thin chips as they have different physical properties compared to their bulky counterparts. Also, transistors and other active devices on UTCs experiencing variable bending stresses will suffer from the piezoresistive effect of silicon substrate which results in a shift of their operating point and therefore, an additional aspect should be considered during circuit design. This thesis tries to address some of these challenges related to UTC technology by focusing initially on modelling of transistors on mechanically bendable Si-UTCs. The developed behavioural models are a combination of mathematical equations and extracted parameters from BSIM4 and BSIM6 modified by a set of equations describing the bending-induced stresses on silicon. The transistor models are written in Verilog-A and compiled in Cadence Virtuoso environment where they were simulated at different bending conditions. To complement this, the verification of these models through experimental results is also presented. Two chips were designed using a 180 nm CMOS technology. The first chip includes nMOS and pMOS transistors with fixed channel width and two different channel lengths and two different channel orientations (0° and 90°) with respect to the wafer crystal orientation. The second chip includes inverter logic gates with different transistor sizes and orientations, as in the previous chip. Both chips were thinned down to ∼20m using dicing-before-grinding (DBG) prior to electrical characterisation at different bending conditions. Furthermore, this thesis presents the first reported fully integrated CMOS-based ISFET microsystem on UTC technology. The design of the integrated CMOS-based ISFET chip with 512 integrated on-chip ISFET sensors along with their read-out and digitisation scheme is presented. The integrated circuits (ICs) are thinned down to ∼30m and the bulky, as well as thinned ICs, are electrically and electrochemically characterised. Also, the thesis presents the first reported mechanically bendable CMOS-based ISFET device demonstrating that mechanical deformation of the die can result in drift compensation through the exploitation of the piezoresistive nature of silicon. Finally, this thesis presents the studies towards the development of on-chip reference electrodes and biodegradable and ultra-thin biosensors for the detection of neurotransmitters such as dopamine and serotonin

Ultra-thin silicon technology for tactile sensors

In order to meet the requirements of high performance flexible electronics in fast growing portable consumer electronics, robotics and new fields such as Internet of Things (IoT), new techniques such as electronics based on nanostructures, molecular electronics and quantum electronics have emerged recently. The importance given to the silicon chips with thickness below 50 μm is particularly interesting as this will advance the 3D IC technology as well as open new directions for high-performance flexible electronics. This doctoral thesis focusses on the development of silicon–based ultra-thin chip (UTC) for the next generation flexible electronics. UTCs, on one hand can provide processing speed at par with state-of-the-art CMOS technology, and on the other provide the mechanical flexibility to allow smooth integration on flexible substrates. These development form the motivation behind the work presented in this thesis. As the thickness of any silicon piece decreases, the flexural rigidity decreases. The flexural rigidity is defined as the force couple required to bend a non-rigid structure to a unit curvature, and therefore the flexibility increases. The new approach presented in this thesis for achieving thin silicon exploits existing and well-established silicon infrastructure, process, and design modules. The thin chips of thicknesses ranging between 15 μm – 30 μm, were obtained from processed bulk wafer using anisotropic chemical etching. The thesis also presents thin wafer transfer using two-step transfer printing approach, packaging by lamination or encapsulation between two flexible layerand methods to get the electrical connections out of the chip. The devices realised on the wafer as part of front-end processing, consisted capacitors and transistors, have been tested to analyse the effect of bending on the electrical characteristics. The capacitance of metal-oxide-semiconductor (MOS) capacitors increases by ~5% during bending and similar shift is observed in flatband and threshold voltages. Similarly, the carrier mobility in the channel region of metal-oxide-semiconductor field effect transistor (MOSFET) increases by 9% in tensile bending and decreases by ~5% in compressive bending. The analytical model developed to capture the effect of banding on device performance showed close matching with the experimental results. In order to employ these devices as tactile sensors, two types of piezoelectric materials are investigated, and used in extended gate configuration with the MOSFET. Firstly, a nanocomposite of Poly(vinylidene fluoride-co-trifluoroethylene), P(VDF-TrFE) and barium titanate (BT) was developed. The composite, due to opposite piezo and pyroelectric coefficients of constituents, was able to suppress the sensitivity towards temperature when force and temperature varied together, The sensitivity to force in extended gate configuration was measured to be 630 mV/N, and sensitivity to temperature was 6.57 mV/oC, when it was varied during force application. The process optimisation for sputtering piezoelectric Aluminium Nitride (AlN) was also carried out with many parametric variation. AlN does not require poling to exhibit piezoelectricity and therefore offers an attractive alternative for the piezoelectric layer used in devices such as POSFET (where piezoelectric material is directly deposited over the gate area of MOSFET). The optimised process gave highly orientated columnar structure AlN with piezoelectric coefficient of 5.9 pC/N and when connected in extended gate configuration, a sensitivity (normalised change in drain current per unit force) of 2.65 N-1 was obtained

Inorganic micro/nanostructures-based high-performance flexible electronics for electronic skin application

Electronics in the future will be printed on diverse substrates, benefiting several emerging applications such as electronic skin (e-skin) for robotics/prosthetics, flexible displays, flexible/conformable biosensors, large area electronics, and implantable devices. For such applications, electronics based on inorganic micro/nanostructures (IMNSs) from high mobility materials such as single crystal silicon and compound semiconductors in the form of ultrathin chips, membranes, nanoribbons (NRs), nanowires (NWs) etc., offer promising high-performance solutions compared to conventional organic materials. This thesis presents an investigation of the various forms of IMNSs for high-performance electronics. Active components (from Silicon) and sensor components (from indium tin oxide (ITO), vanadium pentaoxide (V2O5), and zinc oxide (ZnO)) were realised based on the IMNS for application in artificial tactile skin for prosthetics/robotics. Inspired by human tactile sensing, a capacitive-piezoelectric tandem architecture was realised with indium tin oxide (ITO) on a flexible polymer sheet for achieving static (upto 0.25 kPa-1 sensitivity) and dynamic (2.28 kPa-1 sensitivity) tactile sensing. These passive tactile sensors were interfaced in extended gate mode with flexible high-performance metal oxide semiconductor field effect transistors (MOSFETs) fabricated through a scalable process. The developed process enabled wafer scale transfer of ultrathin chips (UTCs) of silicon with various devices (ultrathin chip resistive samples, metal oxide semiconductor (MOS) capacitors and n‐channel MOSFETs) on flexible substrates up to 4″ diameter. The devices were capable of bending upto 1.437 mm radius of curvature and exhibited surface mobility above 330 cm2/V-s, on-to-off current ratios above 4.32 decades, and a subthreshold slope above 0.98 V/decade, under various bending conditions. While UTCs are useful for realizing high-density high-performance micro-electronics on small areas, high-performance electronics on large area flexible substrates along with low-cost fabrication techniques are also important for realizing e-skin. In this regard, two other IMNS forms are investigated in this thesis, namely, NWs and NRs. The controlled selective source/drain doping needed to obtain transistors from such structure remains a bottleneck during post transfer printing. An attractive solution to address this challenge based on junctionless FETs (JLFETs), is investigated in this thesis via technology computer-aided design (TCAD) simulation and practical fabrication. The TCAD optimization implies a current of 3.36 mA for a 15 μm channel length, 40 μm channel width with an on-to-off ratio of 4.02x 107. Similar to the NRs, NWs are also suitable for realizing high performance e-skin. NWs of various sizes, distribution and length have been fabricated using various nano-patterning methods followed by metal assisted chemical etching (MACE). Synthesis of Si NWs of diameter as low as 10 nm and of aspect ratio more than 200:1 was achieved. Apart from Si NWs, V2O5 and ZnO NWs were also explored for sensor applications. Two approaches were investigated for printing NWs on flexible substrates namely (i) contact printing and (ii) large-area dielectrophoresis (DEP) assisted transfer printing. Both approaches were used to realize electronic layers with high NW density. The former approach resulted in 7 NWs/μm for bottom-up ZnO and 3 NWs/μm for top-down Si NWs while the latter approach resulted in 7 NWs/μm with simultaneous assembly on 30x30 electrode patterns in a 3 cm x 3 cm area. The contact-printing system was used to fabricate ZnO and Si NW-based ultraviolet (UV) photodetectors (PDs) with a Wheatstone bridge (WB) configuration. The assembled V2O5 NWs were used to realize temperature sensors with sensitivity of 0.03% /K. The sensor arrays are suitable for tactile e-skin application. While the above focuses on realizing conventional sensing and addressing elements for e-skin, processing of a large amount of data from e-skin has remained a challenge, especially in the case of large area skin. A Neural NW Field Effect Transistors (υ-NWFETs) based hardware-implementable neural network (HNN) approach for tactile data processing in e-skin is presented in the final part of this thesis. The concept is evaluated by interfacing with a fabricated kirigami-inspired e-skin. Apart from e-skin for prosthetics and robotics, the presented research will also be useful for obtaining high performance flexible circuits needed in many futuristic flexible electronics applications such as smart surgical tools, biosensors, implantable electronics/electroceuticals and flexible mobile phones

Ultra-thin chips for high-performance flexible electronics

Flexible electronics has significantly advanced over the last few years, as devices and circuits from nanoscale structures to printed thin films have started to appear. Simultaneously, the demand for high-performance electronics has also increased because flexible and compact integrated circuits are needed to obtain fully flexible electronic systems. It is challenging to obtain flexible and compact integrated circuits as the silicon based CMOS electronics, which is currently the industry standard for high-performance, is planar and the brittle nature of silicon makes bendability difficult. For this reason, the ultra-thin chips from silicon is gaining interest. This review provides an in-depth analysis of various approaches for obtaining ultra-thin chips from rigid silicon wafer. The comprehensive study presented here includes analysis of ultra-thin chips properties such as the electrical, thermal, optical and mechanical properties, stress modelling, and packaging techniques. The underpinning advances in areas such as sensing, computing, data storage, and energy have been discussed along with several emerging applications (e.g., wearable systems, m-Health, smart cities and Internet of Things etc.) they will enable. This paper is targeted to the readers working in the field of integrated circuits on thin and bendable silicon; but it can be of broad interest to everyone working in the field of flexible electronics

A CMOS Analog Front-End for Tunnelling Magnetoresistive Spintronic Sensing Systems

This paper presents a CMOS readout circuit for an integrated and highly-sensitive tunnel-magnetoresistive (TMR) sensor. Based on the characterization of the TMR sensor in the finite-element simulation, using COMSOL Multiphysics, the circuit including a Wheatstone bridge and an analogue front-end (AFE) circuit, were designed to achieve low-noise and low-power sensing. We present a transimpedance amplifier (TIA) that biases and amplifies a TMR sensor array using switched-capacitors external noise filtering and allows the integration of TMR sensors on CMOS without decreasing the measurement resolution. Designed using TSMC 0.18 μm 1V technology, the amplifier consumes 160 nA at 1.8 V supply to achieve a dc gain of 118 dB and a bandwidth of 3.8 MHz. The results confirm that the full system is able to detect the magnetic field in the pico-Tesla range with low circuit noise (2.297 pA/√Hz) and low power consumption (86 μW). A concurrent reduction in the power consumption and attenuation of noise in TMR sensors makes them suitable for long-term deployment in spintronic sensing systems

Instability and buckling analysis of stretchable silicon system

Ph.DDOCTOR OF PHILOSOPH