Hot-carrier reliability evaluation for CMOS devices and circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.Includes bibliographical references (p. 138-139).by Vei-Han Chan.Ph.D

Simulation and Optimisation of SiGe MOSFETs

This research project is concerned with the development of methodology for simulating advanced SiGe MOSFETs using commercial simulators, the calibration of simulators against higher level Monte Carlo simulation results and real device measurements, and the application of simulation tools in the design of next generation p- channel devices. The methodology for the modelling and simulation of SiGe MOSFET devices is outlined. There are many simulation approaches widely used to simulate SiGe devices, such as Monte Carlo, hydrodynamic, energy transport, and drift diffusion. Different numerical techniques including finite difference, finite box and finite element methods, may be used in the simulators. The Si0.8Ge0.2 p-MOSFETs fabricated especially for high-field transport studies and the Si0.64Ge0.36 p-channel MOSFETs fabricated at Warwick and Southampton Universities with a CMOS compatible process in varying gate lengths were calibrated and investigated. Enhanced low field mobility in SiGe layers compared to Si control devices was observed. The results indicated that the potential of velocity overshoot effects for SiGe p-MOSFETs was considerably higher than Si counterparts, promising higher performance in the former at equal gate lengths at ultra-small devices. The effects of punchthrough stopper, undoped buffers and delta doping for SiGe p-MOSFETs were analysed systematically. It was found that the threshold voltage roll off might be reduced considerably by using an appropriate punchthrough stopper. In order to adjust the threshold voltage for digital CMOS applications, p-type delta doping was required for n+-polysilicon gate p-MOSFET. The use of delta doping made the threshold voltage roll off a more serious issue, therefore delta doping should be used with caution. The two-dimensional process simulator TSUPREM-4 and the two-dimensional device simulator MEDICI were employed to optimise and design Si/SiGe hybrid CMOS. The output of TSUPREM-4 was transferred automatically to the MEDICI device simulator. This made the simulation results more realistic. For devices at small gate length, lightly doped drain (LDD) structures were required. They would decrease the lateral subdiffusion and allow threshold voltage roll off to be minimised. These structures, however, would generally reduce drain current due to an increase in the series resistance of the drain region. Further consideration must be made of these trade-offs. Comparison between drift diffusion and hydrodynamic simulation results for SiGe p-MOSFETs were presented for the first time, with transport parameters extracted from our in-house full-band hole Monte Carlo transport simulator. It was shown that while drift diffusion and hydrodynamic simulations provided a reasonable estimation of the I-V characteristics for Si devices, the same could not be said for aggressively scaled SiGe devices. The resulting high fields at the source end of the devices meant that nonequilibrium transport effects were significant. Therefore for holes, models based on an isotropic carrier temperature were no longer appropriate, as it was shown by analysing the tensor components of the carrier temperature obtained from Monte Carlo simulation. Two-dimensional drift diffusion and Monte Carlo simulations of well-tempered Si p-MOSFETs with gate lengths of 25 and 50 nm were performed. By comparing Monte Carlo simulations with carefully calibrated drift diffusion results, it was found that nonequilibrium transport was important for understanding the high current device characteristics in sub 0.1 mum p-MOSFETs. The well-tempered devices showed better characteristics than the conventional SiGe devices. Both threshold voltage roll off and the subthreshold slope were acceptable although the effective channel length of this device was reduced from 50 nm to 25 nm. In order to adjust the threshold voltage for the digital CMOS applications, p-type delta doping was used for 50 nm well-tempered SiGe p- MOSFETs. As the delta doping made the threshold voltage roll off too serious, it was not suitable for 25 nm well-tempered SiGe p-MOSFETs

Downscaling of 0.35 J.lm to 0.25 J.lm CMOS Transistor by Simulation

Silicon (Si) based integrated circuit (IC) has become the backbone of today's semiconductor world with MOS transistors as its fundamental building blocks. The integrated circuit complexity has moved from the early small-scale integration (SSI) to ultra-large-scale integration (ULSI) that can accommodate millions of transistors on a single chip. This evolution is primarily attributed to the concept of device miniaturization. The resulting scaledown devices do not only improve the packing density but also exhibit enhanced performance in terms of faster switching speed and lower power dissipation. The objective of this work is to perform downscaling of 0.35 Jll11 to 0.25 Jll11 CMOS transistor using Silvaco 2-D ATHENA and ATLAS simulation tool. A "two-step design" approach is proposed in this work to study the feasibility of miniaturization process by scaling method. A scaling factor, K of 1.4 (derived from direct division of 0.35 with 0.25) is adopted for selected parameters. The first design step involves a conversion of the physical data of 0.35 Jll11 CMOS technology to the simulated environment, where process recipe acquired from UC Berkeley Microfabrication Lab serves as the design basis. The electrical data for the simulated structure of 0.35 11m CMOS was extracted with the use of the device simulator. Using the simulated, optimized 0.35 Jll11 structure, downscaling to a smaller geometry of 0.25 Jll11 CMOS transistor was carried out and subsequent electrical characterization was performed in order to evaluate its performance. Parameters that are monitored to evaluate the performance of the designed 0.25 Jll11 CMOS transistor include threshold voltage (VtJJ, saturation current (ldsaJ, off-state leakage current (Ion) and subthreshold swing (SJ. From the simulation, the V1h obtained is of 0.51 V and -0.4 V for NMOS and PMOS respectively, with a difference of 15%-33% as compared to other reported work. However, for results of Idsat. the values obtained which is of 296 ~-tAIJll11 for NMOS and 181 J.lA/Jll11 for PMOS is much lower than other reported work by 28%-50%. This is believed to be due to direct scaling of 0.25 Jll11 transistor from the 0.35 11m geometry without alterations on the existing structure. For Ioffand St. both results show a much better value as compared to other work. I off obtained which is of <1 0 pA/J.lm is about 80%-96% lower than the maximum allowable specification. As for S1, the values obtained which is <90 mY/dec is only within 5% differences as compared to specification. In overall, these results (except for Idsat) accepted values for the particular 0.25 J..Lm technology. From this work, the capability to perform device miniaturization from 0.35 J..Lffi to 0.25 J..Lffi has been developed. This is achieved by acquiring the technical know-how on the important aspects of simulation required for successful simulation of 0.35 J..Lffi technology. Ultimately, the outcome of this work which is a simulated 0.25 J..Lm CMOS transistor can be used as a basis for scaling down to a much smaller device, namely towards 90-nrn geometry

Hot carrier degradation in deep submicron n-MOS technologies

With the aggressive scaling of MOS devices hot carrier degradation continues to be a major reliability concern. The LDD technologies, which have been used to minimise the hot carrier damage in MOS devices, suffer from the spacer damage causing the drain series resistance degradation, along with the channel mobility degradation. Therefore, in order to optimise the performance and reliability of these technologies it is necessary to quantify the roles of spacer and channel damages in determining their degradation behaviour. In this thesis the hot carrier degradation behaviour of different generations of graded drain (lightly doped, mildly doped and highly doped) n-MOS technologies, designed for 5V, 3V and 2V operation is investigated. The stress time beginning from microseconds is investigated to study how the damage initiates and evolves over time. A technology dependent two-stage degradation behaviour in the measured transconductance with an early stage deviating from conventionally observed power law behaviour is reported. A methodology based on conventional extraction procedure using the L-array method is first developed to analyse the drain series resistance and the mobility degradation. For 5V technologies the analysis of the damage using this methodology shows a two-stage drain series resistance degradation with early stage lasting about lOOms. However, it is seen that the conventional series resistance and mobility degradation methodology fails to satisfactorily predict degradation behaviour of 3V and 2V technologies, resulting in unphysical decreasing extracted series resistance. It is shown that after the hot carrier stress a change in the universal mobility behaviour for channel lengths approaching quarter micron regime has a significant effect on the parameter extraction. A modified universal mobility model incorporating the effect of the interface charge is developed using the FN stress experiments. A new generalised extraction methodology modelling hot carrier stressed device as series combination of undamaged and damaged channel regions, along with the series source drain resistance is developed, incorporating the modified universal model in the damaged channel region. The new methodology has the advantage of being single device based and serves as an effective tool in evaluating. the roles of series resistance and mobility degradations for technology qualification. This is especially true for the deep submicron regime where the conventional extraction procedures are not applicable. Further, the new extraction method has the potential of being integrated into commercial device simulation tools, to accurately analyse the device degradation behaviour in deep submicron regime

Cmos Rf Cituits Sic] Variability And Reliability Resilient Design, Modeling, And Simulation

The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. The results show that the biasing design helps improve the robustness of the PA in terms of linear gain, P1dB, Psat, and power added efficiency (PAE). Except for post-fabrication calibration capability, the design reduces the majority performance sensitivity of PA by 50% when subjected to threshold voltage (VT) shift and 25% to electron mobility (μn) degradation. The impact of degradation mismatches is also investigated. It is observed that the accelerated aging of MOS transistor in the biasing circuit will further reduce the sensitivity of PA. In the study of LNA, a 24 GHz narrow band cascade LNA with adaptive biasing scheme under various aging rate is compared to LNA without such biasing scheme. The modeling and simulation results show that the adaptive substrate biasing reduces the sensitivity of noise figure and minimum noise figure subject to process variation and iii device aging such as threshold voltage shift and electron mobility degradation. Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability

Statistical compact model strategies for nano CMOS transistors subject of atomic scale variability

One of the major limiting factors of the CMOS device, circuit and system simulation in sub 100nm regimes is the statistical variability introduced by the discreteness of charge and granularity of matter. The statistical variability cannot be eliminated by tuning the layout or by tightening fabrication process control. Since the compact models are the key bridge between technology and design, it is necessary to transfer reliably the MOSFET statistical variability information into compact models to facilitate variability aware design practice. The aim of this project is the development of a statistical extraction methodology essential to capture statistical variability with optimum set of parameters particularly in industry standard compact model BSIM. This task is accomplished by using a detailed study on the sensitivity analysis of the transistor current in respect to key parameters in compact model in combination with error analysis of the fitted Id-Vg characteristics. The key point in the developed direct statistical compact model strategy is that the impacts of statistical variability can be captured in device characteristics by tuning a limited number of parameters and keeping the values for remaining major set equal to their default values obtained from the “uniform” MOSFET compact model extraction. However, the statistical compact model extraction strategies will accurately represent the distribution and correlation of the electrical MOSFET figures of merit. Statistical compact model parameters are generated using statistical parameter generation techniques such as uncorrelated parameter distributions, principal component analysis and nonlinear power method. The accuracy of these methods is evaluated in comparison with the results obtained from ‘atomistic’ simulations. The impact of the correlations in the compact model parameters has been analyzed along with the corresponding transistor figures of merit. The accuracy of the circuit simulations with different statistical compact model libraries has been studied. Moreover, the impact of the MOSFET width/length on the statistical trend of the optimum set of statistical compact model parameters and electrical figures of merit has been analyzed with two methods to capture geometry dependencies in proposed statistical models

Design of Nanoscale MOSFETs and Characterization of their Performance by Device Simulations

東洋大学201