454 research outputs found

    Modelling of field-effect transistors based on 2D materials targeting high-frequency applications

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    New technologies are necessary for the unprecedented expansion of connectivity and communications in the modern technological society. The specific needs of wireless communication systems in 5G and beyond, as well as devices for the future deployment of Internet of Things has caused that the International Technology Roadmap for Semiconductors, which is the strategic planning document of the semiconductor industry, considered since 2011, graphene and related materials (GRMs) as promising candidates for the future of electronics. Graphene, a one-atom-thick of carbon, is a promising material for high-frequency applications due to its intrinsic superior carrier mobility and very high saturation velocity. These exceptional carrier transport properties suggest that GRM-based field-effect transistors could potentially outperform other technologies. This thesis presents a body of work on the modelling, performance prediction and simulation of GRM-based field-effect transistors and circuits. The main goal of this work is to provide models and tools to ease the following issues: (i) gaining technological control of single layer and bilayer graphene devices and, more generally, devices based on 2D materials, (ii) assessment of radio-frequency (RF) performance and microwave stability, (iii) benchmarking against other existing technologies, (iv) providing guidance for device and circuit design, (v) simulation of circuits formed by GRM-based transistors.Comment: Thesis, 164 pages, http://hdl.handle.net/10803/40531

    DESIGN, COMPACT MODELING AND CHARACTERIZATION OF NANOSCALE DEVICES

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    Electronic device modeling is a crucial step in the advancement of modern nanotechnology and is gaining more and more interest. Nanoscale complementary metal oxide semiconductor (CMOS) transistors, being the backbone of the electronic industry, are pushed to below 10 nm dimensions using novel manufacturing techniques including extreme lithography. As their dimensions are pushed into such unprecedented limits, their behavior is still captured using models that are decades old. Among many other proposed nanoscale devices, silicon vacuum electron devices are regaining attention due to their presumed advantages in operating at very high power, high speed and under harsh environment, where CMOS cannot compete. Another type of devices that have the potential to complement CMOS transistors are nano-electromechanical systems (NEMS), with potential applications in filters, stable frequency sources, non-volatile memories and reconfigurable and neuromorphic electronics

    Compact Modeling Technology for the Simulation of Integrated Circuits Based on Graphene Field-Effect Transistors

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    The progress made toward the definition of a modular compact modeling technology for graphene field-effect transistors (GFETs) that enables the electrical analysis of arbitrary GFET-based integrated circuits is reported. A set of primary models embracing the main physical principles defines the ideal GFET response under DC, transient (time domain), AC (frequency domain), and noise (frequency domain) analysis. Another set of secondary models accounts for the GFET non-idealities, such as extrinsic-, short-channel-, trapping/detrapping-, self-heating-, and non-quasi static-effects, which can have a significant impact under static and/or dynamic operation. At both device and circuit levels, significant consistency is demonstrated between the simulation output and experimental data for relevant operating conditions. Additionally, a perspective of the challenges during the scale up of the GFET modeling technology toward higher technology readiness levels while drawing a collaborative scenario among fabrication technology groups, modeling groups, and circuit designers, is provided.European Commission 881603Spanish Government European Commission RTI2018-097876-B-C21 European CommissionDepartament de Recerca i Universitat 001-P-00170

    Design methodology for graphene tunable filters at the sub–millimeter–wave frequencies

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    Tunable components and circuits, allowing for the fast switching between the states of operation, are among the basic building blocks for future communications and other emerging applications. Based on the previous thorough study of graphene based resonators, the design methodology for graphene tunable filters has been devised, outlined, as well as explained through an example of the fifth order filter. The desired filtering responses can be achieved with the material loss not higher than the loss corresponding to the previously studied single resonators, depending mostly on the quantity of graphene per resonator. The proposed design method relies on the detailed design space mapping; obtained data gives an immediate assessment of the feasibility of specifications with a particular filter order, maximal passband ripple level, desired bandwidth, and acceptable losses. The design process could be further automated by the knowledge based approach using the collected design space data

    Agenda: Second International Workshop on Thin Films for Electronics, Electro-Optics, Energy and Sensors (TFE3S)

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    University of Dayton’s Center of Excellence for Thin Film Research and Surface Engineering (CETRASE) is delighted to organize its second international workshop at the University of Dayton’s Research Institute (UDRI) campus in Dayton, Ohio, USA. The purpose of the new workshop is to exchange technical knowledge and boost technical and educational collaboration activities within the thin film research community through our CETRASE and the UDRI
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