Characterization of Thin Pixel Sensor Modules Interconnected with SLID Technology Irradiated to a Fluence of 2⋅1015\cdot 10^{15}\,neq_{\mathrm{eq}}/cm2^2

A new module concept for future ATLAS pixel detector upgrades is presented, where thin n-in-p silicon sensors are connected to the front-end chip exploiting the novel Solid Liquid Interdiffusion technique (SLID) and the signals are read out via Inter Chip Vias (ICV) etched through the front-end. This should serve as a proof of principle for future four-side buttable pixel assemblies for the ATLAS upgrades, without the cantilever presently needed in the chip for the wire bonding. The SLID interconnection, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It is characterized by a very thin eutectic Cu-Sn alloy and allows for stacking of different layers of chips on top of the first one, without destroying the pre-existing bonds. This paves the way for vertical integration technologies. Results of the characterization of the first pixel modules interconnected through SLID as well as of one sample irradiated to $2\cdot10^{15}$\,\neqcm{} are discussed. Additionally, the etching of ICV into the front-end wafers was started. ICVs will be used to route the signals vertically through the front-end chip, to newly created pads on the backside. In the EMFT approach the chip wafer is thinned to (50--60)\,$\mu$m.Comment: Proceedings to PSD

Production and Characterisation of SLID Interconnected n-in-p Pixel Modules with 75 Micrometer Thin Silicon Sensors

The performance of pixel modules built from 75 micrometer thin silicon sensors and ATLAS read-out chips employing the Solid Liquid InterDiffusion (SLID) interconnection technology is presented. This technology, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It allows for stacking of different interconnected chip and sensor layers without destroying the already formed bonds. In combination with Inter-Chip-Vias (ICVs) this paves the way for vertical integration. Both technologies are combined in a pixel module concept which is the basis for the modules discussed in this paper. Mechanical and electrical parameters of pixel modules employing both SLID interconnections and sensors of 75 micrometer thickness are covered. The mechanical features discussed include the interconnection efficiency, alignment precision and mechanical strength. The electrical properties comprise the leakage currents, tuning characteristics, charge collection, cluster sizes and hit efficiencies. Targeting at a usage at the high luminosity upgrade of the LHC accelerator called HL-LHC, the results were obtained before and after irradiation up to fluences of $10^{16}$ $\mathrm{n}_{\mathrm{eq}}/\mathrm{cm}^2$ (1 MeV neutrons).Comment: 16 pages, 22 figure

Recent Results of the ATLAS Upgrade Planar Pixel Sensors R&D Project

To cope with the higher occupancy and radiation damage at the HL-LHC also the LHC experiments will be upgraded. The ATLAS Planar Pixel Sensor R&D Project (PPS) is an international collaboration of 17 institutions and more than 80 scientists, exploring the feasibility of employing planar pixel sensors for this scenario. Depending on the radius, different pixel concepts are investigated using laboratory and beam test measurements. At small radii the extreme radiation environment and strong space constraints are addressed with very thin pixel sensors active thickness in the range of (75-150) mum, and the development of slim as well as active edges. At larger radii the main challenge is the cost reduction to allow for instrumenting the large area of (7-10) m^2. To reach this goal the pixel productions are being transferred to 6 inch production lines and more cost-efficient and industrialised interconnection techniques are investigated. Additionally, the n-in-p technology is employed, which requires less production steps since it relies on a single-sided process. Recent accomplishments obtained within the PPS are presented. The performance in terms of charge collection and efficiency, obtained with radioactive sources in the laboratory and at beam tests, is presented for devices built from sensors of different vendors connected to either the present ATLAS chip FE-I3 or the new Insertable B-Layer chip FE-I4. The devices, with a thickness varying between 75 mum and 300 mum, were irradiated to several fluences up to 2e16 neq/cm. Finally, the different approaches followed inside the collaboration to achieve slim or active edges are presented.Comment: Proceedings for the Pixel 2012, 7 pages, 6 figures, accepted by NIM

Achievements of the ATLAS Upgrade Planar Pixel Sensors R&D Project

To extend the physics reach of the LHC, accelerator upgrades are planned which will increase the integrated luminosity to beyond 3000 fb^-1 and the pile-up per bunch-crossing by a factor 5 to 10. To cope with the increased occupancy and radiation damage, the ATLAS experiment plans to introduce an all-silicon inner tracker with the HL-LHC upgrade. To investigate the suitability of pixel sensors using the proven planar technology for the upgraded tracker, the ATLAS Upgrade Planar Pixel Sensor R&D Project (PPS) was established comprising 19 institutes and more than 80 scientists. Main areas of research are the performance assessment of planar pixel sensors with different designs and substrate thicknesses up to the HL-LHC fluence, the achievement of slim or active edges to provide low geometric inefficiencies without the need for shingling of modules and the exploration of possibilities for cost reduction to enable the instrumentation of large areas. This paper gives an overview of recent accomplishments and ongoing work of the R&D project

Heavily Irradiated N-in-p Thin Planar Pixel Sensors with and without Active Edges

We present the results of the characterization of silicon pixel modules employing n-in-p planar sensors with an active thickness of 150 $\mathrm{\mu}$m, produced at MPP/HLL, and 100-200 $\mathrm{\mu}$m thin active edge sensor devices, produced at VTT in Finland. These thin sensors are designed as candidates for the ATLAS pixel detector upgrade to be operated at the HL-LHC, as they ensure radiation hardness at high fluences. They are interconnected to the ATLAS FE-I3 and FE-I4 read-out chips. Moreover, the n-in-p technology only requires a single side processing and thereby it is a cost-effective alternative to the n-in-n pixel technology presently employed in the LHC experiments. High precision beam test measurements of the hit efficiency have been performed on these devices both at the CERN SpS and at DESY, Hamburg. We studied the behavior of these sensors at different bias voltages and different beam incident angles up to the maximum one expected for the new Insertable B-Layer of ATLAS and for HL-LHC detectors. Results obtained with 150 $\mathrm{\mu}$m thin sensors, assembled with the new ATLAS FE-I4 chip and irradiated up to a fluence of 4$\times$10$^{15}\mathrm{n}_{\mathrm{eq}}/\mathrm{cm}^2$, show that they are excellent candidates for larger radii of the silicon pixel tracker in the upgrade of the ATLAS detector at HL-LHC. In addition, the active edge technology of the VTT devices maximizes the active area of the sensor and reduces the material budget to suit the requirements for the innermost layers. The edge pixel performance of VTT modules has been investigated at beam test experiments and the analysis after irradiation up to a fluence of 5$\times$10$^{15}\mathrm{n}_{\mathrm{eq}}/\mathrm{cm}^2$ has been performed using radioactive sources in the laboratory.Comment: Proceedings for iWoRiD 2013 conference, submitted to JINS

Low mass hybrid pixel detectors for the high luminosity LHC upgrade

Reducing material in silicon trackers is of major importance for a good overall detector performance, and poses severe challenges to the design of the tracking system. To match the low mass constraints for trackers in High Energy Physics experiments at high luminosity, dedicated technological developments are required. This dissertation presents three technologies to design low mass hybrid pixel detectors for the high luminosity upgrades of the LHC. The work targets specifically the reduction of the material from the detector services and modules, with novel powering schemes, flip chip and interconnection technologies. A serial powering scheme is prototyped, featuring a new regulator concept, a control and protection element, and AC-coupled data transmission. A modified flip chip technology is developed for thin, large area Front-End chips, and a via last Through Silicon Via process is demonstrated on existing pixel modules. These technologies, their developments, and the achievable material reduction are discussed using the upgrades of the ATLAS pixel detector as a case study

Topical Workshop on Electronics for Particle Physics

The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities