Hardware Software Co-Simulation and Real-Time Video Processing For Edge Detection Using Matlab Simulink Model Blockset

FPGA can be useful in many different applications, such as developing more complex systems to be compatible. Using the blocks designed by Xilinx for its System Generator software, a simple algorithm can be designed and tested using Simulink and an FPGA development board, for example edge detection algorithm. Edge detection of image significantly reduces the amount of data and filters out unwanted or insignificant information and gives the significant information in an image. Implementing edge detection is not limited to software development but also hardware development. Edge detection implemented in hardware have emerged as the most viable solution for improving the performance of image processing systems.   This application note will make use of the Spartan-3A DSP development board to explain how to co-simulate Xilinx’s highest level form of an Edgefilter on a still image and implementation sobel edge detection on real-time video based on FPGA board. This document begins by explaining how to convert a still image into a format useable by Matlab and Simulink, shows the construction of a basic algorithm using Xilinx’s System Generator blocks, and also illustrates the procedure of implementing the design real-time video processing using the FPGA development board. The light condition and color contrast will affect the edge detection result. The result of this implementation is detecting edges from the real-time video that has been captured by the camera. Keywords: Sobel Fiter, Edge Detection, Co-simulation, FPGA, Matlab, Simulin

A Hardware-in-the-Loop Platform for DC Protection

With the proliferation of power electronics, dc-based power distribution systems can be realized; however, dc electrical protection remains a significant barrier to mass implementation dc power distribution. Controller Hardware-in-the-loop (CHiL) simulation enables moving up technology readiness levels (TRL) quickly. This work presents an end-to-end solution for dc protection CHiL for early design exploration and verification for dc protection, allowing for the rapid development of dc protection schemes for both Line-to-Line (LL) and Line-to-Ground (LG) faults. The approach combines using Latency Based Linear Multistep Compound (LB-LMC), a real-time simulation method for power electronic, and National Instruments (NI) FPGA hardware to enable dc protection design with CHiL. A case study is performed for a 1.5 MW Voltage Source Rectifier (VSR) under LL and LG faults in an ungrounded system. The deficiency in real-time simulation resolution of Commercial-off-the-Shelf (COTS) for dc fault transients is shown, and addressed by using LB-LMC RT solver inside NI FPGA hardware to achieve 50 ns resolution of dc fault transients

FPGA-Based Implementation of Finite Set-MPC for a VSI System Using XSG-Based Modeling

Finite set-model predictive control (FS-MPC) is used for power converters and drives having unique advantages as compared to the conventional control strategies. However, the computational burden of the FS-MPC is a primary concern for real-time implementation. Field programmable gate array (FPGA) is an alternative and exciting solution for real-time implementation because of the parallel processing capability, as well as, discrete nature of the hardware platform. Nevertheless, FPGA is capable of handling the computational requirements for the FS-MPC implementation, however, the system development involves multiple steps that lead to the time-consuming debugging process. Moreover, specific hardware coding skill makes it more complex corresponding to an increase in system complexity that leads to a tedious task for system development. This paper presents an FPGA-based experimental implementation of FS-MPC using the system modeling approach. Furthermore, a comparative analysis of FS-MPC in stationary αβ and rotating dq frame is considered for simulation as well as experimental result. The FS-MPC for a three-phase voltage source inverter (VSI) system is developed in a realistic digital simulator integrated with MATLAB-Simulink. The simulated controller model is further used for experimental system implementation and validation using Xilinx FPGA: Zedboard Zynq Evaluation and Development Kit. The digital simulator termed as Xilinx system generator (XSG) provided by Xilinx is used for modeling-based FPGA design

GPU-based implementation of real-time system for spiking neural networks

Real-time simulations of biological neural networks (BNNs) provide a natural platform for applications in a variety of fields: data classification and pattern recognition, prediction and estimation, signal processing, control and robotics, prosthetics, neurological and neuroscientific modeling. BNNs possess inherently parallel architecture and operate in continuous signal domain. Spiking neural networks (SNNs) are type of BNNs with reduced signal dynamic range: communication between neurons occurs by means of time-stamped events (spikes). SNNs allow reduction of algorithmic complexity and communication data size at a price of little loss in accuracy. Simulation of SNNs using traditional sequential computer architectures results in significant time penalty. This penalty prohibits application of SNNs in real-time systems. Graphical processing units (GPUs) are cost effective devices specifically designed to exploit parallel shared memory-based floating point operations applied not only to computer graphics, but also to scientific computations. This makes them an attractive solution for SNN simulation compared to that of FPGA, ASIC and cluster message passing computing systems. Successful implementations of GPU-based SNN simulations have been already reported. The contribution of this thesis is the development of a scalable GPU-based realtime system that provides initial framework for design and application of SNNs in various domains. The system delivers an interface that establishes communication with neurons in the network as well as visualizes the outcome produced by the network. Accuracy of the simulation is emphasized due to its importance in the systems that exploit spike time dependent plasticity, classical conditioning and learning. As a result, a small network of 3840 Izhikevich neurons implemented as a hybrid system with Parker-Sochacki numerical integration method achieves real time operation on GTX260 device. An application case study of the system modeling receptor layer of retina is reviewed

Novel implementation technique for a wavelet-based broadband signal detection system

This thesis reports on the design, simulation and implementation of a novel Implementation for a Wavelet-based Broadband Signal Detection System. There is a strong interest in methods of increasing the resolution of sonar systems for the detection of targets at sea. A novel implementation of a wideband active sonar signal detection system is proposed in this project. In the system the Continuous Wavelet Transform is used for target motion estimation and an Adaptive-Network-based Fuzzy inference System (ANFIS) is adopted to minimize the noise effect on target detection. A local optimum search algorithm is introduced in this project to reduce the computation load of the Continuous Wavelet Transform and make it suitable for practical applications. The proposed system is realized on a Xilinx University Program Virtex-II Pro Development System which contains a Virtex II pro XC2VP30 FPGA chip with 2 powerPC 405 cores. Testing for single target detection and multiple target detection shows the proposed system is able to accurately locate targets under reverberation-limited underwater environment with a Signal-Noise-Ratio of up to -30db, with location error less than 10 meters and velocity estimation error less than 1 knot. In the proposed system the combination of CWT and local optimum search algorithm significantly saves the computation time for CWT and make it more practical to real applications. Also the implementation of ANFIS on the FPGA board indicates in the future a real-time ANFIS operation with VLSI implementation would be possible

Wireless multi-carrier communication system design and implementation using a custom hardware and software FPGA platform

Field Programmable Gate Array (FPGA) devices and high-level hardware development languages represent a new and exciting addition to traditional research tools, where simulation models can be evaluated by the direct implementation of complex algorithms and processes. Signal processing functions that are based on well known and standardised mathematical operations, such as Fast Fourier Transforms (FFTs), are well suited for FPGA implementation. At UCL, research is on-going on the design, modelling and simulation of Frequency Division Multiplexing (FDM) techniques such as Spectrally E - cient Frequency Division Multiplexing (SEFDM) which, for a given data rate, require less bandwidth relative to equivalent Orthogonal Frequency Division Multiplexing (OFDM). SEFDM is based around standard mathematical functions and is an ideal candidate for FPGA implementation. The aim of the research and engineering work reported in this thesis is to design and implement a system that generates SEFDM signals for the purposes of testing and veri cation, in real communication environments. The aim is to use FPGA hardware and Digital to Analogue Converters (DACs) to generate such signals and allow recon gurability using standard interfaces and user friendly software. The thesis details the conceptualisation, design and build of an FPGA-based wireless signal generation platform. The characterisation applied to the system, using the FPGA to drive stimulus signals is reported and the thesis will include details of the FPGA encapsulation of the minimum protocol elements required for communication (of control signals) over Ethernet. Detailed testing of the hardware is reported, together with a newly designed in the loop testing methodology. Veri ed test results are also reported with full details of time and frequency results as well as full FPGA design assessment. Altogether, the thesis describes the engineering design, construction and testing of a new FPGA hardware and software system for use in communication test scenarios, controlled over Ethernet

Fast Simulation of Electromagnetic Transients in Power Systems:Numerical Solvers and their Coupling with the Electromagnetic Time Reversal Process

The development of modern and future power systems is associated with the definition of new approaches for their simulation, control, and protection. To give an example, the increasing connection of massive renewable energy conversion systems is justifying the integration of DC infrastructures (eventually, multi-terminal HVDC) in the current AC power grids. Furthermore, the existing passive distribution networks are evolving by integration of decentralized and intermittent generation units which results in Active Distribution Networks (ADNs). As a consequence, complex power system topologies are emerging requiring adequate simulation tools capable to reproduce, possibly in real-time, their dynamic behavior. In this context, future operation/protection practices of power networks might rely on the availability of chip-scale real-time simulators (RTS) that will enable the implementation of efficient protection/fault location processes that, in principle, should be capable to comply with the restrictive constraints associated with these complex systems. Within this context, the work presented in the thesis contributes to the integration of new concepts of the fault location in AC/DC systems that can be deployed in chip-scale real-time simulation hardware represented by Field Programmable Gate Arrays (FPGAs). The development of the proposed fault location platform is done in two steps. First, an original fault location method based on the Electromagnetic Time Reversal (EMTR) theory is proposed. The proposed method is validated for the case of various power networks topologies and its performance is assessed. Compared to the existing fault location methods, the proposed approach is suitably applicable to different topologies including MTDCs and ADNs. Next, a new automated FPGA-based solver for RTS is proposed. The developed FPGA-RTS uses a specific automated procedure to couple the simulation platform with an offline simulation environment (EMTR-RV) without the need for Hardware Description Language (HDL). It is able to simulate both power electronics converters and power system grids and thanks to the use of particular parallel computational algorithms, it can accurately simulate, in real-time, Electromagnetic Transient (EMT) phenomena taking place in power converters and travelling wave propagation along multi-conductor transmission lines within very small simulation time steps (in the order of some hundreds of nanoseconds). To overcome the limitations associated with the Fixed Admittance Matrix Nodal Method (FAMNM), a method to assess the optimal value of the parameter of the Associated Discrete Circuit (ADC) switch model used by FAMNM is proposed. Finally, a specific application of the developed FPGA-RTS is explored for the development of a fault location platform by leveraging the EMTR theory. To this end, the proposed EMTR-based fault location method is integrated with the FPGA-RTS to develop an efficient fault location platform. Thanks to the fast EMT simulation capability of the FPGA-RTS, the developed fault location platform is able to estimate the accurate fault location within very short time scales. Moreover, the developed platform is compatible with the constraints characterizing complex topologies such as MTDC networks (e.g., the ultra-fast operation of the protection systems). The developed fault location platform is validated by making reference to an MTDC grid and an ADN, and it is shown to exhibit remarkable fault location accuracy as well as robustness against uncertainties such as fault type, the presence of noise, measurement systems delay, and fault impedance

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

© 2016 Cheung, Schultz and Luk.NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation