Role of Optical Network in Cloud/Fog Computing

This chapter is a study of exploring the role of the optical network in the cloud/fog computing environment. With the growing network issues, unified and cost-effective computing services and efficient utilization of optical resources are required for building smart applications. Fog computing provides the foundation platform for implementing cyber-physical system (CPS) applications which require ultra-low latency. Also, the digital revolution of fog/cloud computing using optical resources has upgraded the education system by intertwined VR using the fog nodes. Presently, the current technologies face many challenges such as ultra-low delay, optimum bandwidth, and minimum energy consumption to promote virtual reality (VR)-based and electroencephalogram (EEG)-based gaming applications. Ultra-low delay, optimum bandwidth, and minimum energy consumption. Therefore, an Optical-Fog layer is introduced to provide a novel, secure, highly distributed, and ultra-dense fog computing infrastructure. Also, for optimum utilization of optical resources, a novel concept of OpticalFogNode is introduced that provides computation and storage capabilities at the Optical-Fog layer in the software defined networking (SDN)-based optical network. It efficiently facilitates the dynamic deployment of new distributed SDN-based OpticalFogNode which supports low-latency services with minimum energy as well as bandwidth usage. Therefore, an EEG-based VR framework is also introduced that uses the resources of the optical network in the cloud/fog computing environment

A sub-mW IoT-endnode for always-on visual monitoring and smart triggering

This work presents a fully-programmable Internet of Things (IoT) visual sensing node that targets sub-mW power consumption in always-on monitoring scenarios. The system features a spatial-contrast $128\mathrm{x}64$ binary pixel imager with focal-plane processing. The sensor, when working at its lowest power mode ($10\mu W$ at 10 fps), provides as output the number of changed pixels. Based on this information, a dedicated camera interface, implemented on a low-power FPGA, wakes up an ultra-low-power parallel processing unit to extract context-aware visual information. We evaluate the smart sensor on three always-on visual triggering application scenarios. Triggering accuracy comparable to RGB image sensors is achieved at nominal lighting conditions, while consuming an average power between $193\mu W$ and $277\mu W$, depending on context activity. The digital sub-system is extremely flexible, thanks to a fully-programmable digital signal processing engine, but still achieves 19x lower power consumption compared to MCU-based cameras with significantly lower on-board computing capabilities.Comment: 11 pages, 9 figures, submitteted to IEEE IoT Journa

Very Low Power Neural Network FPGA Accelerators for Tag-Less Remote Person Identification Using Capacitive Sensors

Human detection, identification, and monitoring are essential for many applications aiming to make smarter the indoor environments, where most people spend much of their time (like home, office, transportation, or public spaces). The capacitive sensors can meet stringent privacy, power, cost, and unobtrusiveness requirements, they do not rely on wearables or specific human interactions, but they may need significant on-board data processing to increase their performance. We comparatively analyze in terms of overall processing time and energy several data processing implementations of multilayer perceptron neural networks (NNs) on board capacitive sensors. The NN architecture, optimized using augmented experimental data, consists of six 17-bit inputs, two hidden layers with eight neurons each, and one four-bit output. For the software (SW) NN implementation, we use two STMicroelectronics STM32 low-power ARM microcontrollers (MCUs): one MCU optimized for power and one for performance. For hardware (HW) implementations, we use four ultralow-power field-programmable gate arrays (FPGAs), with different sizes, dedicated computation blocks, and data communication interfaces (one FPGA from the Lattice iCE40 family and three FPGAs from the Microsemi IGLOO family). Our shortest SW implementation latency is 54.4 µs and the lowest energy per inference is 990 nJ, while the shortest HW implementation latency is 1.99 µs and the lowest energy is 39 nJ (including the data transfer between MCU and FPGA). The FPGAs active power ranges between 6.24 and 34.7 mW, while their static power is between 79 and 277 µW. They compare very favorably with the static power consumption of Xilinx and Altera low-power device families, which is around 40 mW. The experimental results show that NN inferences offloaded to external FPGAs have lower latency and energy than SW ones (even when using HW multipliers), and the FPGAs with dedicated computational blocks (multiply-accumulate) perform best

Wireless Sensor Needs Defined by SBIR Topics

This slide presentation reviews the needs for wireless sensor technology from various U.S. government agencies as exhibited by an analysis of Small Business Innovation Research (SBIR) solicitations. It would appear that a multi-agency group looking at overlapping wireless sensor needs and technology projects is desired. Included in this presentation is a review of the NASA SBIR process, and an examination of some of the SBIR projects from NASA, and other agencies that involve wireless sensor developmen

Aerospace medicine and biology: A continuing bibliography with indexes, supplement 183

This bibliography lists 273 reports, articles, and other documents introduced into the NASA scientific and technical information system in July 1978

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

Implementing embedded neural network processing at the edge requires efficient hardware acceleration that couples high computational performance with low power consumption. Driven by the rapid evolution of network architectures and their algorithmic features, accelerator designs are constantly updated and improved. To evaluate and compare hardware design choices, designers can refer to a myriad of accelerator implementations in the literature. Surveys provide an overview of these works but are often limited to system-level and benchmark-specific performance metrics, making it difficult to quantitatively compare the individual effect of each utilized optimization technique. This complicates the evaluation of optimizations for new accelerator designs, slowing-down the research progress. This work provides a survey of neural network accelerator optimization approaches that have been used in recent works and reports their individual effects on edge processing performance. It presents the list of optimizations and their quantitative effects as a construction kit, allowing to assess the design choices for each building block separately. Reported optimizations range from up to 10'000x memory savings to 33x energy reductions, providing chip designers an overview of design choices for implementing efficient low power neural network accelerators

Energy challenges for ICT

The energy consumption from the expanding use of information and communications technology (ICT) is unsustainable with present drivers, and it will impact heavily on the future climate change. However, ICT devices have the potential to contribute signi - cantly to the reduction of CO2 emission and enhance resource e ciency in other sectors, e.g., transportation (through intelligent transportation and advanced driver assistance systems and self-driving vehicles), heating (through smart building control), and manu- facturing (through digital automation based on smart autonomous sensors). To address the energy sustainability of ICT and capture the full potential of ICT in resource e - ciency, a multidisciplinary ICT-energy community needs to be brought together cover- ing devices, microarchitectures, ultra large-scale integration (ULSI), high-performance computing (HPC), energy harvesting, energy storage, system design, embedded sys- tems, e cient electronics, static analysis, and computation. In this chapter, we introduce challenges and opportunities in this emerging eld and a common framework to strive towards energy-sustainable ICT

Integration of Renewables in Power Systems by Multi-Energy System Interaction

This book focuses on the interaction between different energy vectors, that is, between electrical, thermal, gas, and transportation systems, with the purpose of optimizing the planning and operation of future energy systems. More and more renewable energy is integrated into the electrical system, and to optimize its usage and ensure that its full production can be hosted and utilized, the power system has to be controlled in a more flexible manner. In order not to overload the electrical distribution grids, the new large loads have to be controlled using demand response, perchance through a hierarchical control set-up where some controls are dependent on price signals from the spot and balancing markets. In addition, by performing local real-time control and coordination based on local voltage or system frequency measurements, the grid hosting limits are not violated