626 research outputs found

    Integral formulation of the measured equation of invariance

    Get PDF
    A novel integral formulation of the measured equation of invariance is derived from the reciprocity theorem. This formulation leads to a sparse matrix equation for the induced surface current, resulting in great CPU time and memory savings over the conventional approaches. The algorithm has been implemented for two-dimensional perfectly conducting scatterers.Peer ReviewedPostprint (published version

    0.5V 3rd-order Tunable gm-C Filter

    Get PDF
    This paper proposes a 3rd-order gm-C filter that operates with the extremely low voltage supply of 0.5V. The employed transconductor is capable for operating in an extremely low voltage power supply environment. A benefit offered by the employed transconductor is that the filter’s cut-off frequency can be tuned, through a dc control current, for relatively large ranges. The filter structure was designed using normal threshold transistors of a triple-well 0.13ÎŒm CMOS process and is operated under a 0.5V supply voltage; its behavior has been evaluated through simulation results by utilizing the Analog Design Environment of the Cadence software

    Oscillation-based DFT for Second-order Bandpass OTA-C Filters

    Get PDF
    This document is the Accepted Manuscript version. Under embargo until 6 September 2018. The final publication is available at Springer via https://doi.org/10.1007/s00034-017-0648-9.This paper describes a design for testability technique for second-order bandpass operational transconductance amplifier and capacitor filters using an oscillation-based test topology. The oscillation-based test structure is a vectorless output test strategy easily extendable to built-in self-test. The proposed methodology converts filter under test into a quadrature oscillator using very simple techniques and measures the output frequency. Using feedback loops with nonlinear block, the filter-to-oscillator conversion techniques easily convert the bandpass OTA-C filter into an oscillator. With a minimum number of extra components, the proposed scheme requires a negligible area overhead. The validity of the proposed method has been verified using comparison between faulty and fault-free simulation results of Tow-Thomas and KHN OTA-C filters. Simulation results in 0.25ÎŒm CMOS technology show that the proposed oscillation-based test strategy for OTA-C filters is suitable for catastrophic and parametric faults testing and also effective in detecting single and multiple faults with high fault coverage.Peer reviewedFinal Accepted Versio

    Design of high frequency transconductor ladder filters

    Get PDF

    High Input Impedance Voltage-Mode Biquad Filter Using VD-DIBAs

    Get PDF
    This paper deals with a single-input multiple-output biquadratic filter providing three functions (low-pass, high-pass and band-pass) based on voltage differencing differential input buffered amplifier (VD-DIBA). The quality factor and pole frequency can be electronically tuned via the bias current. The proposed circuit uses two VD-DIBAs and two grounded capacitors without any external resistors, which is suitable to further develop into an integrated circuit. Moreover, the circuit possesses high input impedance, providing easy voltage-mode cascading. It is shown that the filter structure can be easily extended to multi-input filter without any additional components, providing also all-pass and band-reject properties. The PSPICE simulation and experimental results are included, verifying the key characteristics of the proposed filter. The given results agree well with the theoretical presumptions

    Dual-mode multifunction filter realized with a single voltage differencing gain amplifier (VDGA)

    Get PDF
    This article presents the dual-mode multifunction biquad filter realized employing only a single voltage differencing gain amplifier (VDGA), one resistor and three capacitors. The proposed filterwith one input and three outputs can configure as voltage-mode or current-mode filter circuit with the appropriate input injection choice. It can also synthesis the three standard filter functions, which are highpass, bandpass, and lowpass responses without modifying the circuit configuration. Orthogonal adjustment between the natural angular frequency (o) and the quality factor (Q) of the filter is achieved. Detail analysis of non-ideal VDGA effects and circuit component sensitivity are included. The circuit principle is verified by means of simulation results with TSMC 0.35-m CMOS process parameters

    A wideband linear tunable CDTA and its application in field programmable analogue array

    Get PDF
    This document is the Accepted Manuscript version of the following article: Hu, Z., Wang, C., Sun, J. et al. ‘A wideband linear tunable CDTA and its application in field programmable analogue array’, Analog Integrated Circuits and Signal Processing, Vol. 88 (3): 465-483, September 2016. Under embargo. Embargo end date: 6 June 2017. The final publication is available at Springer via https://link.springer.com/article/10.1007%2Fs10470-016-0772-7 © Springer Science+Business Media New York 2016In this paper, a NMOS-based wideband low power and linear tunable transconductance current differencing transconductance amplifier (CDTA) is presented. Based on the NMOS CDTA, a novel simple and easily reconfigurable configurable analogue block (CAB) is designed. Moreover, using the novel CAB, a simple and versatile butterfly-shaped FPAA structure is introduced. The FPAA consists of six identical CABs, and it could realize six order current-mode low pass filter, second order current-mode universal filter, current-mode quadrature oscillator, current-mode multi-phase oscillator and current-mode multiplier for analog signal processing. The Cadence IC Design Tools 5.1.41 post-layout simulation and measurement results are included to confirm the theory.Peer reviewedFinal Accepted Versio

    Strategies for enhancing DC gain and settling performance of amplifiers

    Get PDF
    The operational amplifier (op amp) is one of the most widely used and important building blocks in analog circuit design. High gain and high speed are two important properties of op amps because they determine the settling behavior of the op amps. As supply voltages decrease, the realization of high gain amplifiers with large Gain-Bandwidth-Products (GBW) has become challenging. The major focus in this dissertation is on the negative output impedance gain enhancement technique. The negative impedance gain enhancement technique offers potential for achieving very high gain and energy-efficient fast settling and is low-voltage compatible. Misconceptions that have limited the practical adoption of this gain enhancement technique are discussed. A new negative conductance gain enhancement technique was proposed. The proposed circuit generates a negative conductance with matching requirements for achieving very high DC gain that are less stringent than those for existing -g m gain enhancement schemes. The proposed circuit has potential for precise digital control of a very large DC gain. A prototype fully differential CMOS operational amplifier was designed and fabricated based on the proposed gain enhancement technique. Experimental results which showed a DC gain of 85dB and an output swing of 876mVp-p validated the fundamental performance characteristics of this technique. In a separate section, a new amplifier architecture with bandpass feedforward compensation is presented. It is shown that a bandpass feedforward path can be used to substantially extend the unity-gain-frequency of an operational amplifier. Simulation results predict significant improvements in rise time and settling performance and show that the bandpass compensation scheme is reasonably robust. In the final section, a new technique for asynchronous data recovery based upon using a delay line in the incoming data path is introduced. The proposed data recovery system is well suited for tight tolerance channels and coding systems supporting standards that limit the maximum number of consecutive 0\u27s and 1\u27s in a data stream. This system does not require clock recovery, suffers no loss of data during acquisition, has a reduced sensitivity to jitter in the incoming data and does not exhibit jitter enhancement associated with VCO tracking in a PLL
    • 

    corecore