Deterministic Constructions for Large Girth Protograph LDPC Codes

The bit-error threshold of the standard ensemble of Low Density Parity Check (LDPC) codes is known to be close to capacity, if there is a non-zero fraction of degree-two bit nodes. However, the degree-two bit nodes preclude the possibility of a block-error threshold. Interestingly, LDPC codes constructed using protographs allow the possibility of having both degree-two bit nodes and a block-error threshold. In this paper, we analyze density evolution for protograph LDPC codes over the binary erasure channel and show that their bit-error probability decreases double exponentially with the number of iterations when the erasure probability is below the bit-error threshold and long chain of degree-two variable nodes are avoided in the protograph. We present deterministic constructions of such protograph LDPC codes with girth logarithmic in blocklength, resulting in an exponential fall in bit-error probability below the threshold. We provide optimized protographs, whose block-error thresholds are better than that of the standard ensemble with minimum bit-node degree three. These protograph LDPC codes are theoretically of great interest, and have applications, for instance, in coding with strong secrecy over wiretap channels.Comment: 5 pages, 2 figures; To appear in ISIT 2013; Minor changes in presentatio

Near-capacity fixed-rate and rateless channel code constructions

Fixed-rate and rateless channel code constructions are designed for satisfying conflicting design tradeoffs, leading to codes that benefit from practical implementations, whilst offering a good bit error ratio (BER) and block error ratio (BLER) performance. More explicitly, two novel low-density parity-check code (LDPC) constructions are proposed; the first construction constitutes a family of quasi-cyclic protograph LDPC codes, which has a Vandermonde-like parity-check matrix (PCM). The second construction constitutes a specific class of protograph LDPC codes, which are termed as multilevel structured (MLS) LDPC codes. These codes possess a PCM construction that allows the coexistence of both pseudo-randomness as well as a structure requiring a reduced memory. More importantly, it is also demonstrated that these benefits accrue without any compromise in the attainable BER/BLER performance. We also present the novel concept of separating multiple users by means of user-specific channel codes, which is referred to as channel code division multiple access (CCDMA), and provide an example based on MLS LDPC codes. In particular, we circumvent the difficulty of having potentially high memory requirements, while ensuring that each user’s bits in the CCDMA system are equally protected. With regards to rateless channel coding, we propose a novel family of codes, which we refer to as reconfigurable rateless codes, that are capable of not only varying their code-rate but also to adaptively modify their encoding/decoding strategy according to the near-instantaneous channel conditions. We demonstrate that the proposed reconfigurable rateless codes are capable of shaping their own degree distribution according to the nearinstantaneous requirements imposed by the channel, but without any explicit channel knowledge at the transmitter. Additionally, a generalised transmit preprocessing aided closed-loop downlink multiple-input multiple-output (MIMO) system is presented, in which both the channel coding components as well as the linear transmit precoder exploit the knowledge of the channel state information (CSI). More explicitly, we embed a rateless code in a MIMO transmit preprocessing scheme, in order to attain near-capacity performance across a wide range of channel signal-to-ratios (SNRs), rather than only at a specific SNR. The performance of our scheme is further enhanced with the aid of a technique, referred to as pilot symbol assisted rateless (PSAR) coding, whereby a predetermined fraction of pilot bits is appropriately interspersed with the original information bits at the channel coding stage, instead of multiplexing pilots at the modulation stage, as in classic pilot symbol assisted modulation (PSAM). We subsequently demonstrate that the PSAR code-aided transmit preprocessing scheme succeeds in gleaning more information from the inserted pilots than the classic PSAM technique, because the pilot bits are not only useful for sounding the channel at the receiver but also beneficial for significantly reducing the computational complexity of the rateless channel decoder

An Efficient Algorithm for Counting Cycles in QC and APM LDPC Codes

In this paper, a new method is given for counting cycles in the Tanner graph of a (Type-I) quasi-cyclic (QC) low-density parity-check (LDPC) code which the complexity mainly is dependent on the base matrix, independent from the CPM-size of the constructed code. Interestingly, for large CPM-sizes, in comparison of the existing methods, this algorithm is the first approach which efficiently counts the cycles in the Tanner graphs of QC-LDPC codes. In fact, the algorithm recursively counts the cycles in the parity-check matrix column-by-column by finding all non-isomorph tailless backtrackless closed (TBC) walks in the base graph and enumerating theoretically their corresponding cycles in the same equivalent class. Moreover, this approach can be modified in few steps to find the cycle distributions of a class of LDPC codes based on Affine permutation matrices (APM-LDPC codes). Interestingly, unlike the existing methods which count the cycles up to $2g-2$, where $g$ is the girth, the proposed algorithm can be used to enumerate the cycles of arbitrary length in the Tanner graph. Moreover, the proposed cycle searching algorithm improves upon various previously known methods, in terms of computational complexity and memory requirements.Comment: 18 pages, 4 figure

4-Cycle Free Spatially Coupled LDPC Codes with an Explicit Construction

Spatially coupled low-density parity-check (SC-LDPC) codes are a class of capacity approaching LDPC codes with low message recovery latency when a sliding window decoding is used. In this paper, we first present a new method for the construction of a class of SC-LDPC codes by the incidence matrices of a given non-negative integer matrix $E$, and then the relationship of 4-cycles between matrix $E$ and the corresponding SC-LDPC code are investigated. Finally, by defining a new class of integer finite sequences, called {\it good sequences}, for the first time, we give an explicit method for the construction of a class of 4-cycle free SC-LDPC codes that can achieve (in most cases) the minimum coupling width

Spatially Coupled LDPC Codes Constructed from Protographs

In this paper, we construct protograph-based spatially coupled low-density parity-check (SC-LDPC) codes by coupling together a series of L disjoint, or uncoupled, LDPC code Tanner graphs into a single coupled chain. By varying L, we obtain a flexible family of code ensembles with varying rates and frame lengths that can share the same encoding and decoding architecture for arbitrary L. We demonstrate that the resulting codes combine the best features of optimized irregular and regular codes in one design: capacity approaching iterative belief propagation (BP) decoding thresholds and linear growth of minimum distance with block length. In particular, we show that, for sufficiently large L, the BP thresholds on both the binary erasure channel (BEC) and the binary-input additive white Gaussian noise channel (AWGNC) saturate to a particular value significantly better than the BP decoding threshold and numerically indistinguishable from the optimal maximum a-posteriori (MAP) decoding threshold of the uncoupled LDPC code. When all variable nodes in the coupled chain have degree greater than two, asymptotically the error probability converges at least doubly exponentially with decoding iterations and we obtain sequences of asymptotically good LDPC codes with fast convergence rates and BP thresholds close to the Shannon limit. Further, the gap to capacity decreases as the density of the graph increases, opening up a new way to construct capacity achieving codes on memoryless binary-input symmetric-output (MBS) channels with low-complexity BP decoding.Comment: Submitted to the IEEE Transactions on Information Theor

Multilevel Structured Low-Density Parity-Check Codes

Low-Density Parity-Check (LDPC) codes are typically characterized by a relatively high-complexity description, since a considerable amount of memory is required in order to store their code description, which can be represented either by the connections of the edges in their Tanner graph or by the non-zero entries in their parity-check matrix (PCM). This problem becomes more pronounced for pseudo-random LDPC codes, where literally each non-zero entry of their PCM has to be enumerated, and stored in a look-up table. Therefore, they become inadequate for employment in memoryconstrained transceivers. Motivated by this, we are proposing a novel family of structured LDPC codes, termed as Multilevel Structured (MLS) LDPC codes, which benefit from reduced storage requirements, hardware-friendly implementations as well as from low-complexity encoding and decoding. Our simulation results demonstrate that these advantages accrue without any compromise in their attainable Bit Error Ratio (BER) performance, when compared to their previously proposed more complex counterparts of the same code-length. In particular, we characterize a half-rate quasi-cyclic (QC) MLS LDPC code having a block length of 8064 that can be uniquely and unambiguously described by as few as 144 edges, despite exhibiting an identical BER performance over both Additive White Gaussian Noise (AWGN) and uncorrelated Rayleigh (UR) channels, when compared to a pseudorandom construction, which requires the enumeration of a significantly higher number of 24,192 edges