Oscillation-based DFT for Second-order Bandpass OTA-C Filters

This document is the Accepted Manuscript version. Under embargo until 6 September 2018. The final publication is available at Springer via https://doi.org/10.1007/s00034-017-0648-9.This paper describes a design for testability technique for second-order bandpass operational transconductance amplifier and capacitor filters using an oscillation-based test topology. The oscillation-based test structure is a vectorless output test strategy easily extendable to built-in self-test. The proposed methodology converts filter under test into a quadrature oscillator using very simple techniques and measures the output frequency. Using feedback loops with nonlinear block, the filter-to-oscillator conversion techniques easily convert the bandpass OTA-C filter into an oscillator. With a minimum number of extra components, the proposed scheme requires a negligible area overhead. The validity of the proposed method has been verified using comparison between faulty and fault-free simulation results of Tow-Thomas and KHN OTA-C filters. Simulation results in 0.25μm CMOS technology show that the proposed oscillation-based test strategy for OTA-C filters is suitable for catastrophic and parametric faults testing and also effective in detecting single and multiple faults with high fault coverage.Peer reviewedFinal Accepted Versio

Design for testability of high-order OTA-C filters

Copyright © 2016 John Wiley & Sons, Ltd.A study of oscillation-based test for high-order Operational Transconductance Amplifier-C (OTA-C) filters is presented. The method is based on partition of a high-order filter into second-order filter functions. The opening Q-loop and adding positive feedback techniques are developed to convert the second-order filter section into a quadrature oscillator. These techniques are based on an open-loop configuration and an additional positive feedback configuration. Implementation of the two testability design methods for nth-order cascade, IFLF and leapfrog (LF) filters is presented, and the area overhead of the modified circuits is also discussed. The performances of the presented techniques are investigated. Fourth-order cascade, inverse follow-the-leader feedback (IFLF) and LF OTA-C filters were designed and simulated for analysis of fault coverage using the adding positive feedback method based on an analogue multiplexer. Simulation results show that the oscillation-based test method using positive feedback provides high fault coverage of around 97%, 96% and 95% for the cascade, IFLF and LF OTA-C filters, respectively. Copyright ÂPeer reviewe

Oscillation-Based Test Structure and Method for OTA-C Filters

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”This paper describes a design for testability technique for operational transconductance amplifier and capacitor filters using an oscillation-based test topology. The oscillation-based test structure is a vectorless output test strategy easily extendable to built-in self-test. The proposed methodology converts filter under test into a quadrature oscillator using very simple techniques and measures the output frequency. The oscillation frequency may be considered as a digital signal and it can be evaluated using digital circuitry therefore the test time is very small. These characteristics imply that the proposed method is very suitable for catastrophic and parametric faults testing and also effective in detecting single and multiple faults. The validity of the proposed method has been verified using comparison between faulty and fault-free simulation results of two integrator loop and Tow-Thomas filters. Simulation results in 0.25 mum CMOS technology show that the proposed oscillation-based test strategy for OTA-C filters has 87% fault coverage and with a minimum number of extra components, requires a negligible area overhead

Oscillation-based Test Method for Continuous-time OTA-C Filters

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”Design for testability technique using oscillation-based test topology for KHN OTA-C filters is proposed. The oscillation-based test structure is a vectorless output test strategy easily extendable to built-in self-test. During test mode, the filter under test is converted into an oscillator by establishing the oscillation condition in its transfer function. The oscillator frequency can be measured using digital circuitry and deviations from the cut-off frequency indicate the faulty behaviour of the filter. The proposed method is suitable for both catastrophic and parametric fault diagnosis as well as effective in detecting single and multiple faults. The validity of the proposed method has been verified using comparison between faulty and fault-free simulation results of KHN OTA-C filter. Simulation results in 0.25mum CMOS technology show that the proposed oscillation-based test strategy has 84% fault coverage and with a minimum number of extra components, requires a negligible area overhead.Final Published versio

Layout level design for testability strategy applied to a CMOS cell library

The layout level design for testability (LLDFT) rules used here allow to avoid some hard to detect faults or even undetectable faults on a cell library by modifying the cell layout without changing their behavior and achieving a good level of reliability. These rules avoid some open faults or reduce their appearance probability. The main purpose has been to apply that set of LLDFT rules on the cells of the library designed at the Centre Nacional de Microelectronica (CNM) in order to obtain a highly testable cell library. The authors summarize the main results (area overhead and performance degradation) of the application of the LLDFT rules on the cell

New Aspects of Fault Diagnosis of Nonlinear Analog Circuits

The paper is focused on nonlinear analog circuits, with the special attention paid to circuits comprising bipolar and MOS transistors manufactured in micrometer and submicrometer technology. The problem of fault diagnosis of this class of circuits is discussed, including locating faulty elements and evaluating their parameters. The paper deals with multiple parametric fault diagnosis using the simulation after test approach as well as detection and location of single catastrophic faults, using the simulation before test approach. The discussed methods are based on diagnostic test, leading to a system of nonlinear algebraic type equations, which are not given in explicit analytical form. An important and new aspect of the fault diagnosis is finding multiple solutions of the test equation, i.e. several sets of the parameters values that meet the test. Another new problems in this area are global fault diagnosis of technological parameters in CMOS circuits fabricated in submicrometer technology and testing the circuits  having multiple DC operating points. To solve these problems several methods have been recently developed, which employ  different concepts and mathematical tools of nonlinear analysis. In this paper they are sketched and illustrated.  All the discussed methods are based on the homotopy (continuation) idea. It is shown that various versions of homotopy and combinations  of the homotopy with some other mathematical algorithms lead to very powerful tools for fault diagnosis of nonlinear analog circuits.  To trace the homotopy path which allows finding multiple solutions, the simplicial method, the restart method, the theory of linear complementarity problem and Lemke's algorithm are employed. For illustration four numerical examples are given

Testability enhancement of a basic set of CMOS cells

Testing should be evaluated as the ability of the test patterns to cover realistic faults, and high quality IC products demand high quality testing. We use a test strategy based on physical design for testability (to discover both open and short faults, which are difficult or even impossible to detect). Consequentially, layout level design for testability (LLDFT) rules have been developed, which prevent the faults, or at least reduce the chance of their appearing. The main purpose of this work is to apply a practical set of LLDFT rules to the library cells designed by the Centre Nacional de Microelectrònica (CNM) and obtain a highly testable cell library. The main results of the application of the LLDFT rules (area overheads and performance degradation) are summarized and the results are significant since IC design is highly repetitive; a small effort to improve cell layout can bring about great improvement in design

Influence of material quality and process-induced defects on semiconductor device performance and yield

An overview of major causes of device yield degradation is presented. The relationships of device types to critical processes and typical defects are discussed, and the influence of the defect on device yield and performance is demonstrated. Various defect characterization techniques are described and applied. A correlation of device failure, defect type, and cause of defect is presented in tabular form with accompanying illustrations

A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente