Reliability Analysis of Hafnium Oxide Dielectric Based Nanoelectronics

With the physical dimensions ever scaling down, the increasing level of sophistication in nano-electronics requires a comprehensive and multidisciplinary reliability investigation. A kind of nano-devices, HfO2-based high-k dielectric films, are studied in the statistical aspect of reliability as well as electrical and physical aspects of reliability characterization, including charge trapping and degradation mechanisms, breakdown modes and bathtub failure rate estimation. This research characterizes charge trapping and investigates degradation mechanisms in high-k dielectrics. Positive charges trapped in both bulk and interface contribute to the interface state generation and flat band voltage shift when electrons are injected from the gate under a negative gate bias condition.A negligible number of defects are generated until the stress voltage increases to a certain level. As results of hot electrons and positive charges trapped in the interface region, the difference in the breakdown sequence is attributed to the physical thickness of the bulk high-k layer and the structure of the interface layer. Time-to-breakdown data collected in the accelerated life tests are modeled with a bathtub failure rate curve by a 3-step Bayesian approach. Rather than individually considering each stress level in accelerating life tests (ALT), this approach derives the change point and the priors for Bayesian analysis from the time-to-failure data under neighborhood stresses, based on the relationship between the lifetime and stress voltage. This method can provide a fast and reliable estimation of failure rate for burn-in optimization when only a small sample of data is available

Low Energy Ion Beam Synthesis of SiNanocrystals for Nonvolatile Memories – Modeling and Process Simulations

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Low Energy Ion Beam Synthesis of Si Nanocrystals for Nonvolatile Memories - Modeling and Process Simulations

Metal-Oxide-Silicon Field-Effect-Transistors with a layer of electrically isolated Si nanocrystals (NCs) embedded in the gate oxide are known to improve conventional floating gate flash memories. Data retention, program and erase speeds as well as the memory operation voltages can be substantially improved due to the discrete charge storage in the isolated Si NCs. Using ion beam synthesis, Si NCs can be fabricated along with standard CMOS processing. The optimization of the location and size of ion beam synthesized Si NCs requires a deeper understanding of the mechanisms involved, which determine (i) the built-up of Si supersaturation by high-fluence ion implantation and (ii) NC formation by phase separation. For that aim, process simulations have been conducted that address both aspects on a fundamental level and, on the other hand, are able to avoid tedious experiments. The built-up of a Si supersaturation by high-fluence ion implantation were studied using dynamic binary collision calculations with TRIDYN and have lead to a prediction of Si excess depth profiles in thin gate oxides of a remarkable quality. These simulations include in a natural manner high fluence implantation effects as target erosion by sputtering, target swelling and ion beam mixing. The second stage of ion beam synthesis is modeled with the help of a tailored kinetic Monte Carlo code that combines a detailed kinetic description of phase separation on atomic level with the required degree of abstraction that is necessary to span the timescales involved. Large ensembles of Si NCs were simulated reaching the late stages of NC formation and dissolution at simulation sizes that allowed a direct comparison with experimental studies, e.g. with electron energy loss resolved TEM investigations. These comparisons reveal a nice degree of agreement, e.g. in terms of predicted and observed precipitate morphologies for different ion fluences. However, they also point clearly onto impact of additional external influences as, e.g., the oxidation of implanted Si by absorbed humidity, which was identified with the help of these process simulations. Moreover, these simulations are utilized as a general tool to identify optimum processing regimes for a tailored Si NC formation for NC memories. It is shown that key properties for NC memories as the tunneling distance from the transistor channel to the Si NCs, the NC morphology, size and density can be adjusted accurately despite of the involved degree of self-organization. Furthermore, possible lateral electron tunneling between neighboring Si NCs is evaluated on the basis of the performed kinetic Monte Carlo simulations

Institute of Ion Beam Physics and Materials Research: Annual Report 2002

Summary of the scientific activities of the institute in 2002 including selected highlight reports, short research contributions and an extended statistics overview

Conductance quantization in resistive random access memory

The intrinsic scaling-down ability, simple metal-insulator-metal (MIM) sandwich structure, excellent performances, and complementary metal-oxide-semiconductor (CMOS) technology-compatible fabrication processes make resistive random access memory (RRAM) one of the most promising candidates for the next-generation memory. The RRAM device also exhibits rich electrical, thermal, magnetic, and optical effects, in close correlation with the abundant resistive switching (RS) materials, metal-oxide interface, and multiple RS mechanisms including the formation/rupture of nanoscale to atomic-sized conductive filament (CF) incorporated in RS layer. Conductance quantization effect has been observed in the atomic-sized CF in RRAM, which provides a good opportunity to deeply investigate the RS mechanism in mesoscopic dimension. In this review paper, the operating principles of RRAM are introduced first, followed by the summarization of the basic conductance quantization phenomenon in RRAM and the related RS mechanisms, device structures, and material system. Then, we discuss the theory and modeling of quantum transport in RRAM. Finally, we present the opportunities and challenges in quantized RRAM devices and our views on the future prospects

Resistance switching devices based on amorphous insulator-metal thin films

Nanometallic devices based on amorphous insulator-metal thin films are developed to provide a novel non-volatile resistance-switching random-access memory (RRAM). In these devices, data recording is controlled by a bipolar voltage, which tunes electron localization length, thus resistivity, through electron trapping/detrapping. The low-resistance state is a metallic state while the high-resistance state is an insulating state, as established by conductivity studies from 2K to 300K. The material is exemplified by a Si3N4 thin film with randomly dispersed Pt or Cr. It has been extended to other materials, spanning a large library of oxide and nitride insulator films, dispersed with transition and main-group metal atoms. Nanometallic RRAMs have superior properties that set them apart from other RRAMs. The critical switching voltage is independent of the film thickness/device area/temperature/switching speed. Trapped electrons are relaxed by electron-phonon interaction, adding stability which enables long-term memory retention. As electron-phonon interaction is mechanically altered, trapped electron can be destabilized, and sub-picosecond switching has been demonstrated using an electromagnetically generated stress pulse. AC impedance spectroscopy confirms the resistance state is spatially uniform, providing a capacitance that linearly scales with area and inversely scales with thickness. The spatial uniformity is also manifested in outstanding uniformity of switching properties. Device degradation, due to moisture, electrode oxidation and dielectrophoresis, is minimal when dense thin films are used or when a hermetic seal is provided. The potential for low power operation, multi-bit storage and complementary stacking have been demonstrated in various RRAM configurations.Comment: 523 pages, 215 figures, 10 chapter

Functional nanoelectronic devices: single-electron transport, memristivity, and thermoelectricity in nanoscale flms using self-assembly and graphene

This dissertation reports on several experimental projects studying electronic transport in thin-flm electronic devices. Self-assembly methods and graphene were used to realise devices contacting films of self-assembled PbS quantum dots. The devices have exhibited single-electron tunnelling with a high yield. The electrical properties of the junctions are studied individually and collectively using statistical tools to extract correlations between device geometries and electrical data. The dissertation includes discussion of the theory of relevant electronic transport including numerical simulations. Several initiated projects deriving from this work are introduced. A second device reported in this thesis is a memristive switch. Contacting thin films of Al2O3 with graphene delivered junctions which exhibit memristive behaviour with an ultrahigh on-off conductance ratio. The conduction state of the junctions is correlated with morphological changes in the devices, whereby conductive flament formation in the junction is found to lead to electrically-controllable and reversible gas encapsulation in bubbles in the structure. The device is measured electrically and topographically, and the correlation between the two aspects is studied. A discussion of memristive conduction is included with numerical simulations. A third section reports on a project studying thermoelectricity in self-assembled molecular junctions, as they show potential for improved thermoelectric efficiency for energy harvesting; this is discussed in the dissertation. Strategies to benchmark the studies are presented with relevant devices fabricated and measured. These include the development of a measurement protocol to study thermoelectricity in devices, studies of electrical coupling between various molecular structures and graphene electrodes, molecular-structure dependence of electrical and thermal conductance of junctions. Preliminary results and on-going work are discussed.I want to thank the Semiconductor Physics Group of the Cavendish Laboratory, the Semiconductor Physics Group of the Institute of Physics, the Cambridge NanoDTC, and Fitzwilliam College, Cambridge for their support. I want also to thank the collaborators acknowledged in the thesis for contributions in materials and services