Arc fault detection using artificial intelligence: Challenges and benefits

This systematic review aims to investigate recent developments in the area of arc fault detection. The rising demand for electricity and concomitant expansion of energy systems has resulted in a heightened risk of arc faults and the likelihood of related fires, presenting a matter of considerable concern. To address this challenge, this review focuses on the role of artificial intelligence (AI) in arc fault detection, with the objective of illuminating its advantages and identifying current limitations. Through a meticulous literature selection process, a total of 63 articles were included in the final analysis. The findings of this review suggest that AI plays a significant role in enhancing the accuracy and speed of detection and allowing for customization to specific types of faults in arc fault detection. Simultaneously, three major challenges were also identified, including missed and false detections, the restricted application of neural networks and the paucity of relevant data. In conclusion, AI has exhibited tremendous potential for transforming the field of arc fault detection and holds substantial promise for enhancing electrical safety

Memory Protection in a Real-Time Operating System

During the last years the number of Electrical Control Units (ECU) in vehicles have increased rapidly with the effect of increasing costs. To meet this trend and reduce costs, applications have to be centralized into more powerful ECUs. This gives rise to new problems such as data and temporal integrity. The thesis gives an introduction to these new problems and a solution based on static time-triggered scheduling combined with memory protection. Memory protection mechanisms and hardware are evaluated, resulting in the recommendation of a platform. The thesis also propose modification and extensions to a real-time operating system used today within the Volvo Group. The work has been conducted at Volvo Technology (VTEC) in Gothenburg. VTEC is a combined research and consulting company within the Volvo Grou

Automatic code generation for security requirements in AUTOSAR based on the Crypto Service Manager

The increasing complexity and autonomy of modern vehicles make security a key issue of the design and development in the automotive industry. A careful analysis of the security requirements and adequate mechanisms for ensuring integrity and confidentiality of data are required to guarantee safety. In the automotive domain, AUTOSAR (AUTomotive Open System ARchitecture) is the standard de facto. It provides a component-based system design at different levels of abstraction. In this thesis a library has been developed to implement the Crypto Service Manager (CSM) of AUTOSAR. It offers a standardized access to cryptographic services for applications. The library is implemented in C language and supports the modules for MAC generation/verification and encryption/decryption, according to the standard. In particular, modelling extensions in AUTOSAR are proposed to address confidentiality and integrity security constraints at the design stage. Software components are automatically extended according to security annotations with security elements (ports and interfaces), used to call the CSM functions

New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs

Tesis por compendio[EN] Relevance of electronics towards safety of common devices has only been growing, as an ever growing stake of the functionality is assigned to them. But of course, this comes along the constant need for higher performances to fulfill such functionality requirements, while keeping power and budget low. In this scenario, industry is struggling to provide a technology which meets all the performance, power and price specifications, at the cost of an increased vulnerability to several types of known faults or the appearance of new ones. To provide a solution for the new and growing faults in the systems, designers have been using traditional techniques from safety-critical applications, which offer in general suboptimal results. In fact, modern embedded architectures offer the possibility of optimizing the dependability properties by enabling the interaction of hardware, firmware and software levels in the process. However, that point is not yet successfully achieved. Advances in every level towards that direction are much needed if flexible, robust, resilient and cost effective fault tolerance is desired. The work presented here focuses on the hardware level, with the background consideration of a potential integration into a holistic approach. The efforts in this thesis have focused several issues: (i) to introduce additional fault models as required for adequate representativity of physical effects blooming in modern manufacturing technologies, (ii) to provide tools and methods to efficiently inject both the proposed models and classical ones, (iii) to analyze the optimum method for assessing the robustness of the systems by using extensive fault injection and later correlation with higher level layers in an effort to cut development time and cost, (iv) to provide new detection methodologies to cope with challenges modeled by proposed fault models, (v) to propose mitigation strategies focused towards tackling such new threat scenarios and (vi) to devise an automated methodology for the deployment of many fault tolerance mechanisms in a systematic robust way. The outcomes of the thesis constitute a suite of tools and methods to help the designer of critical systems in his task to develop robust, validated, and on-time designs tailored to his application.[ES] La relevancia que la electrónica adquiere en la seguridad de los productos ha crecido inexorablemente, puesto que cada vez ésta copa una mayor influencia en la funcionalidad de los mismos. Pero, por supuesto, este hecho viene acompañado de una necesidad constante de mayores prestaciones para cumplir con los requerimientos funcionales, al tiempo que se mantienen los costes y el consumo en unos niveles reducidos. En este escenario, la industria está realizando esfuerzos para proveer una tecnología que cumpla con todas las especificaciones de potencia, consumo y precio, a costa de un incremento en la vulnerabilidad a múltiples tipos de fallos conocidos o la introducción de nuevos. Para ofrecer una solución a los fallos nuevos y crecientes en los sistemas, los diseñadores han recurrido a técnicas tradicionalmente asociadas a sistemas críticos para la seguridad, que ofrecen en general resultados sub-óptimos. De hecho, las arquitecturas empotradas modernas ofrecen la posibilidad de optimizar las propiedades de confiabilidad al habilitar la interacción de los niveles de hardware, firmware y software en el proceso. No obstante, ese punto no está resulto todavía. Se necesitan avances en todos los niveles en la mencionada dirección para poder alcanzar los objetivos de una tolerancia a fallos flexible, robusta, resiliente y a bajo coste. El trabajo presentado aquí se centra en el nivel de hardware, con la consideración de fondo de una potencial integración en una estrategia holística. Los esfuerzos de esta tesis se han centrado en los siguientes aspectos: (i) la introducción de modelos de fallo adicionales requeridos para la representación adecuada de efectos físicos surgentes en las tecnologías de manufactura actuales, (ii) la provisión de herramientas y métodos para la inyección eficiente de los modelos propuestos y de los clásicos, (iii) el análisis del método óptimo para estudiar la robustez de sistemas mediante el uso de inyección de fallos extensiva, y la posterior correlación con capas de más alto nivel en un esfuerzo por recortar el tiempo y coste de desarrollo, (iv) la provisión de nuevos métodos de detección para cubrir los retos planteados por los modelos de fallo propuestos, (v) la propuesta de estrategias de mitigación enfocadas hacia el tratamiento de dichos escenarios de amenaza y (vi) la introducción de una metodología automatizada de despliegue de diversos mecanismos de tolerancia a fallos de forma robusta y sistemática. Los resultados de la presente tesis constituyen un conjunto de herramientas y métodos para ayudar al diseñador de sistemas críticos en su tarea de desarrollo de diseños robustos, validados y en tiempo adaptados a su aplicación.[CA] La rellevància que l'electrònica adquireix en la seguretat dels productes ha crescut inexorablement, puix cada volta més aquesta abasta una major influència en la funcionalitat dels mateixos. Però, per descomptat, aquest fet ve acompanyat d'un constant necessitat de majors prestacions per acomplir els requeriments funcionals, mentre es mantenen els costos i consums en uns nivells reduïts. Donat aquest escenari, la indústria està fent esforços per proveir una tecnologia que complisca amb totes les especificacions de potència, consum i preu, tot a costa d'un increment en la vulnerabilitat a diversos tipus de fallades conegudes, i a la introducció de nous tipus. Per oferir una solució a les noves i creixents fallades als sistemes, els dissenyadors han recorregut a tècniques tradicionalment associades a sistemes crítics per a la seguretat, que en general oferixen resultats sub-òptims. De fet, les arquitectures empotrades modernes oferixen la possibilitat d'optimitzar les propietats de confiabilitat en habilitar la interacció dels nivells de hardware, firmware i software en el procés. Tot i això eixe punt no està resolt encara. Es necessiten avanços a tots els nivells en l'esmentada direcció per poder assolir els objectius d'una tolerància a fallades flexible, robusta, resilient i a baix cost. El treball ací presentat se centra en el nivell de hardware, amb la consideració de fons d'una potencial integració en una estratègia holística. Els esforços d'esta tesi s'han centrat en els següents aspectes: (i) la introducció de models de fallada addicionals requerits per a la representació adequada d'efectes físics que apareixen en les tecnologies de fabricació actuals, (ii) la provisió de ferramentes i mètodes per a la injecció eficient del models proposats i dels clàssics, (iii) l'anàlisi del mètode òptim per estudiar la robustesa de sistemes mitjançant l'ús d'injecció de fallades extensiva, i la posterior correlació amb capes de més alt nivell en un esforç per retallar el temps i cost de desenvolupament, (iv) la provisió de nous mètodes de detecció per cobrir els reptes plantejats pels models de fallades proposats, (v) la proposta d'estratègies de mitigació enfocades cap al tractament dels esmentats escenaris d'amenaça i (vi) la introducció d'una metodologia automatitzada de desplegament de diversos mecanismes de tolerància a fallades de forma robusta i sistemàtica. Els resultats de la present tesi constitueixen un conjunt de ferramentes i mètodes per ajudar el dissenyador de sistemes crítics en la seua tasca de desenvolupament de dissenys robustos, validats i a temps adaptats a la seua aplicació.Espinosa García, J. (2016). New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/73146TESISCompendi

Development of LoRaWAN-based IoT system for water quality monitoring in rural areas

This article delineates the design and deployment of an innovative real-time water quality monitoring system tailored for rural regions, focusing on monitoring the water resource quality parameters. We propose a solar-powered, waterproof, portable, and Internet of Things (IoT)-enabled solution that leverages Long Range Wide Area Network (LoRaWAN) technology. Central to this system is a sophisticated LoRa node outfitted with an array of sensors for capturing key water parameters, such as pH, total dissolved solids, turbidity and temperature. A conjunction of an Arduino microcontroller-based board and a LoRa shield facilitates real-time data capture and transmission to a LoRaWAN gateway. The acquired data is transmitted to The Things Network server, which is seamlessly integrated with a ThingSpeak web-based IoT server and ThingView mobile applications. We incorporate a solar cell with a solar shield to ensure sustainable energy provision for powering the entire system through a rechargeable battery. This allows users to access vital water quality information online simultaneously and continuously in real-time. As a testament to its robustness, the system was empirically tested at Gambang Lake to demonstrate its effectiveness, functionality, buoyancy, and waterproof capabilities. We further validated the results by comparing them with laboratory sample analysis findings. Experimental evaluations confirmed the system's reliability, as evidenced by the strong agreement between the water conditions measured using our solution and those obtained from laboratory instruments. Moreover, our system efficiently and remotely updated data across multiple IoT platforms using the LoRa radio interface over the LoRaWAN gateway

Development of a mechatronic transmission control system for the drivetrain of the K71 project

The tractive force has to be interrupted during a gear-shifting operation in a manual vehicle transmission, leading into a decrease of speed while changing gears during the acceleration process. Therefore in a racing application, the shifting time has to be as short as possible so that the required performance of a racing car can be achieved. The following dissertation describes the development of a transmission control system to enable gear changes within a manual gearbox, which was designed for the Formula Student racing series. Various solutions were developed on the basis of reviewed literature, technical data of components and experiences of Formula Student teams. Following this, a comparison of the concepts by means of a utility analysis identified the pneumatic actuation of selector forks to be the most suitable concept. This was mainly due to the expected shifting time, the weight, and its advantageous energy supply requirement. After the selection of the actuators and the position sensors, the system was implemented into the drivetrain to check the tment and the technical feasibility. To draw conclusions regarding the shifting time and to prove the functionality of the system, an open test bench was constructed. Additionally, the hardware and software had to be developed to enable the test run. After the manufacturing and assembling of the test bench, the optimal settings for the test run were determined. By comparing the achieved shifting time of alternative solutions, an improvement in the driving performance of a Formula Student race car is probable

Arquitecturas de hardware para um veículo eléctrico

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores. Faculdade de Engenharia. Universidade do Porto. 201

POWER QUALITY CONTROL AND COMMON-MODE NOISE MITIGATION FOR INVERTERS IN ELECTRIC VEHICLES

Inverters are widely utilized in electric vehicle (EV) applications as a major voltage/current source for onboard battery chargers (OBC) and motor drive systems. The inverter performance is critical to the efficiency of EV system energy conversion and electronics system electro-magnetic interference (EMI) design. However, for AC systems, the bandwidth requirement is usually low compared with DC systems, and the control impact on the inverter differential-mode (DM) and common-mode (CM) performance are not well investigated. With the wide-band gap (WBG) device era, the switching capability of power electronics devices drastically improved. The DM/CM impact that was brought by the WBG device-based inverter becomes more serious and has not been completely understood. This thesis provides an in-depth analysis of on-board inverter control strategies and the corresponding DM/CM impact on the EV system. The OBC inverter control under vehicle-to-load (V2L) mode will be documented first. A virtual resistance damping method minimizes the nonlinear load harmonics, and a neutral balancing method regulates the unbalanced load impact through the fourth leg. In the motor drive system, a generalized CM voltage analytical model and a current ripple prediction model are built for understanding the system CM and DM stress with respect to different modulation methods, covering both 2-level and 3-level topologies. A novel CM EMI damping modulation scheme is proposed for 6-phase inverter applications. The performance comparison between the proposed methods and the conventional solution is carried out. Each topic is supported by the corresponding hardware platform and experimental validation

Measurement and Analysis of IC Jitters and Soft Failures due to System-level ESD

Department of Electrical EngineeringHuman touches to ground metal of electronic systems can cause electrostatic discharge (ESD)-induced soft failures without causing physical damage. If a number of data are lost due to ESD-induced noises, then a system freeze, fault, or reboot can occur, and user intervention is required to restore normal system operations. Such malfunction of a system is called system-level ESD soft failures that become more serious as the speed of electronic devices increases and their size becomes more compact. Achieving immunity of systems and integrated circuits (ICs) against soft failures due to system-level ESD is an important design goal. In this thesis, two specific circuits whose soft failures can be fatal to whole system are investigated. One of them is a delay-locked loop (DLL) and the other is a sense amplifier flip-flop (SAFF). The DLL is widely used to compensate the timing of high-speed data communications. The SAFF is commonly used as an input receiver for address and command in a DRAM. The DLL and SAFF were designed and fabricated in a 180-nm CMOS process. They are mounted in each simplified design of dual in-line memory module (DIMM) by chip on board (COB) assembly and the DIMMs are mounted on each simplified motherboard. The input and output voltages of the DLL under ESD-induced noises were measured, and the average values of peak-to-peak jitter and jitter durations of the DLL clock were obtained from repeated measurements. The effects of the VDD-GND decoupling capacitors and a bias decoupling capacitor were investigated. The measured DLL output are reproduced in SPICE simulations using the measured DLL input voltages, and the root causes of the jitter are investigated. Additionally, measurements are conducted in a frequency domain to find the relationship between the power-ground impedance and noises. The soft failures of the SAFF due to system-level ESD were investigated under the ESD injection level of 3, 5, and 8 kV. ESD test case without and with VDD-GND decoupling capacitors (de-caps) were investigated. The measurements were conducted 50 times with each test case above. The noise voltages and the soft failure ratio of the SAFF were obtained. SPICE simulation was conducted to validate the results by using measured noise voltages and root causes of the soft failures.clos