3,586 research outputs found
Circuit as Set of Points
As the size of circuit designs continues to grow rapidly, artificial
intelligence technologies are being extensively used in Electronic Design
Automation (EDA) to assist with circuit design. Placement and routing are the
most time-consuming parts of the physical design process, and how to quickly
evaluate the placement has become a hot research topic. Prior works either
transformed circuit designs into images using hand-crafted methods and then
used Convolutional Neural Networks (CNN) to extract features, which are limited
by the quality of the hand-crafted methods and could not achieve end-to-end
training, or treated the circuit design as a graph structure and used Graph
Neural Networks (GNN) to extract features, which require time-consuming
preprocessing. In our work, we propose a novel perspective for circuit design
by treating circuit components as point clouds and using Transformer-based
point cloud perception methods to extract features from the circuit. This
approach enables direct feature extraction from raw data without any
preprocessing, allows for end-to-end training, and results in high performance.
Experimental results show that our method achieves state-of-the-art performance
in congestion prediction tasks on both the CircuitNet and ISPD2015 datasets, as
well as in design rule check (DRC) violation prediction tasks on the CircuitNet
dataset. Our method establishes a bridge between the relatively mature point
cloud perception methods and the fast-developing EDA algorithms, enabling us to
leverage more collective intelligence to solve this task. To facilitate the
research of open EDA design, source codes and pre-trained models are released
at https://github.com/hustvl/circuitformer
AI/ML Algorithms and Applications in VLSI Design and Technology
An evident challenge ahead for the integrated circuit (IC) industry in the
nanometer regime is the investigation and development of methods that can
reduce the design complexity ensuing from growing process variations and
curtail the turnaround time of chip manufacturing. Conventional methodologies
employed for such tasks are largely manual; thus, time-consuming and
resource-intensive. In contrast, the unique learning strategies of artificial
intelligence (AI) provide numerous exciting automated approaches for handling
complex and data-intensive tasks in very-large-scale integration (VLSI) design
and testing. Employing AI and machine learning (ML) algorithms in VLSI design
and manufacturing reduces the time and effort for understanding and processing
the data within and across different abstraction levels via automated learning
algorithms. It, in turn, improves the IC yield and reduces the manufacturing
turnaround time. This paper thoroughly reviews the AI/ML automated approaches
introduced in the past towards VLSI design and manufacturing. Moreover, we
discuss the scope of AI/ML applications in the future at various abstraction
levels to revolutionize the field of VLSI design, aiming for high-speed, highly
intelligent, and efficient implementations
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μ μμ§μΈλ€.Timing analysis and clearing design rule violations are the essential steps for taping out a chip. However, they keep getting harder in deep sub-micron circuits because the variations of transistors and interconnects have been increasing and design rules have become more complex. This dissertation addresses two problems on timing analysis and design rule violations for synthesizing deep sub-micron circuits.
Firstly, timing analysis in process corners can not capture post-Si performance accurately because the slowest path in the process corner is not always the slowest one in the post-Si instances. In addition, the proportion of interconnect delay in the critical path on a chip is increasing and becomes over 20% in sub-10nm technologies, which means in order to capture post-Si performance accurately, the representative critical
path circuit should reflect not only FEOL (front-end-of-line) but also BEOL (backend-of-line) variations. Since the number of BEOL metal layers exceeds ten and the layers have variation on resistance and capacitance intermixed with resistance variation on vias between them, a very high dimensional design space exploration is necessary to synthesize a representative critical path circuit which is able to provide an accurate performance prediction. To cope with this, I propose a BEOL-aware methodology of synthesizing a representative critical path circuit, which is able to incrementally explore, starting from an initial path circuit on the post-Si target circuit, routing patterns (i.e., BEOL reconfiguring) as well as gate resizing on the path circuit. Precisely, the
synthesis framework of critical path circuit integrates a set of novel techniques: (1) extracting and classifying BEOL configurations for lightening design space complexity, (2) formulating BEOL random variables for fast and accurate timing analysis, and (3) exploring alternative (ring oscillator) circuit structures for extending the applicability of this work.
Secondly, the complexity of design rules has been increasing and results in more design rule violations during routing. In addition, the size of standard cell keeps decreasing and it makes routing harder. In the conventional P&R flow, the routability of pre-routed layout is predicted by routing congestion obtained from global routing, and then placement is optimized not to cause design rule violations. But it turned out to be inaccurate in advanced technology nodes so that it is necessary to predict routability with more features. I propose a methodology of predicting the hotspots of design rule violations (DRVs) using machine learning with placement related features and the conventional routing congestion, and perturbating placed cells to reduce the number of DRVs. Precisely, the hotspots are predicted by a pre-trained binary classification model and placement perturbation is performed by global optimization methods to minimize the number of DRVs predicted by a pre-trained regression model. To do this, the framework is composed of three techniques: (1) dividing the circuit layout into multiple rectangular grids and extracting features such as pin density, cell density, global routing results (demand, capacity and overflow), and more in the placement phase, (2) predicting if each grid has DRVs using a binary classification model, and (3) perturbating the placed standard cells in the hotspots to minimize the number of DRVs predicted by a regression model.1 Introduction 1
1.1 Representative Critical Path Circuit . . . . . . . . . . . . . . . . . . . 1
1.2 Prediction of Design Rule Violations and Placement Perturbation . . . 5
1.3 Contributions of This Dissertation . . . . . . . . . . . . . . . . . . . 7
2 Methodology for Synthesizing Representative Critical Path Circuits reflecting BEOL Timing Variation 9
2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Definitions and Overall Flow . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Techniques for BEOL-Aware RCP Generation . . . . . . . . . . . . . 17
2.3.1 Clustering BEOL Configurations . . . . . . . . . . . . . . . . 17
2.3.2 Formulating Statistical BEOL Random Variables . . . . . . . 18
2.3.3 Delay Modeling . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.4 Exploring Ring Oscillator Circuit Structures . . . . . . . . . . 24
2.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.5 Further Study on Variations . . . . . . . . . . . . . . . . . . . . . . . 37
3 Methodology for Reducing Routing Failures through Enhanced Prediction on Design Rule Violations in Placement 39
3.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2 Overall Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.3 Techniques for Reducing Routing Failures . . . . . . . . . . . . . . . 43
3.3.1 Binary Classification . . . . . . . . . . . . . . . . . . . . . . 43
3.3.2 Regression . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.3 Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.4 Placement Perturbation . . . . . . . . . . . . . . . . . . . . . 47
3.4 Experiments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.4.1 Experiments Setup . . . . . . . . . . . . . . . . . . . . . . . 51
3.4.2 Hotspot Prediction . . . . . . . . . . . . . . . . . . . . . . . 51
3.4.3 Regression . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.4.4 Placement Perturbation . . . . . . . . . . . . . . . . . . . . . 57
4 Conclusions 61
4.1 Synthesis of Representative Critical Path Circuits reflecting BEOL Timing Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2 Reduction of Routing Failures through Enhanced Prediction on Design Rule Violations in Placement . . . . . . . . . . . . . . . . . . . . . . 62
Abstract (In Korean) 69Docto
Echo State Networks for Proactive Caching in Cloud-Based Radio Access Networks with Mobile Users
In this paper, the problem of proactive caching is studied for cloud radio
access networks (CRANs). In the studied model, the baseband units (BBUs) can
predict the content request distribution and mobility pattern of each user,
determine which content to cache at remote radio heads and BBUs. This problem
is formulated as an optimization problem which jointly incorporates backhaul
and fronthaul loads and content caching. To solve this problem, an algorithm
that combines the machine learning framework of echo state networks with
sublinear algorithms is proposed. Using echo state networks (ESNs), the BBUs
can predict each user's content request distribution and mobility pattern while
having only limited information on the network's and user's state. In order to
predict each user's periodic mobility pattern with minimal complexity, the
memory capacity of the corresponding ESN is derived for a periodic input. This
memory capacity is shown to be able to record the maximum amount of user
information for the proposed ESN model. Then, a sublinear algorithm is proposed
to determine which content to cache while using limited content request
distribution samples. Simulation results using real data from Youku and the
Beijing University of Posts and Telecommunications show that the proposed
approach yields significant gains, in terms of sum effective capacity, that
reach up to 27.8% and 30.7%, respectively, compared to random caching with
clustering and random caching without clustering algorithm.Comment: Accepted in the IEEE Transactions on Wireless Communication
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