Ono: an open platform for social robotics

In recent times, the focal point of research in robotics has shifted from industrial ro- bots toward robots that interact with humans in an intuitive and safe manner. This evolution has resulted in the subfield of social robotics, which pertains to robots that function in a human environment and that can communicate with humans in an int- uitive way, e.g. with facial expressions. Social robots have the potential to impact many different aspects of our lives, but one particularly promising application is the use of robots in therapy, such as the treatment of children with autism. Unfortunately, many of the existing social robots are neither suited for practical use in therapy nor for large scale studies, mainly because they are expensive, one-of-a-kind robots that are hard to modify to suit a specific need. We created Ono, a social robotics platform, to tackle these issues. Ono is composed entirely from off-the-shelf components and cheap materials, and can be built at a local FabLab at the fraction of the cost of other robots. Ono is also entirely open source and the modular design further encourages modification and reuse of parts of the platform

Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters

In this dissertation, time-based signal processing techniques and their applications in oversampling and noise-shaping data converters are examined. These techniques demonstrate the ability to shift the burden of high performance analog circuits from the compressed voltage-domain to the augmented time-domain. First, the potential of high order noise-shaping and phase-domain feedback in time-to-digital converters (TDCs) is explored. A prototype phase reference, second-order continuous-time delta-sigma TDC for sensor applications was fabricated in 90nm CMOS and achieves 64 dB dynamic range in 1MHz signal bandwidth. Second, an ultra-high performance oscillator-based delta-sigma modulator architecture is investigated. The proposed circuit is a third-order continuous-time PLL-Based Delta-Sigma Modulator with simulated 77 dB SNDR in 40MHz signal bandwidth with OSR of 16, and is fabricated in 65nm CMOS

Design of High Power Converter with SiC MOSFETs

Tato diplomová práce se zabývá návrhem výkonového měniče založeného na topologii typu synchronní buck. Měnič je zkonstruován s využitím MOSFET tranzistorů na bázi silikon karbidu. Tato práce se věnuje analýze měniče s cílem navrhnout a realizovat řídící jednotku umožňující jak zpětnovazební regulaci měniče, tak řízení v otevřené smyčce. Za tímto účelem je odvozen analytický model měniče coby dynamického systému, který je použit pro návrh a simulaci řízení. Kontrolní jednotka je implementována s využitím 32 bitového mikrořadiče založeného na architektuře ARM. V této práci je poskytnut popis a použití klíčových periférií mikrořadiče pro realizaci řízení. Na závěr jsou shrnuty výsledky měření dynamického chování výkonových tranzistorů při provozu měniče. Pozornost je především věnována měření proudu tekoucího jedním tranzistorem s využitím běžného rezistoru pro snímání proudu a kompenzaci frekvenční charakteristiky rezistoru.This master degree thesis is concerned with the design of high power converter. The converter is based on synchronous buck topology and is realized using silicon carbide MOSFET transistors. This work deals with an analysis of such type of converter to design and realize a control unit providing feedback control of the converter. Therefore, a dynamic model of the converter is derived using a conventional technique of averaged state space modeling. The derived model is used for controller design and closed-loop control simulation. The control unit is implemented using a 32-bit ARM-based microcontroller. Hence, an insight into the microcontroller key peripherals is provided as well as a brief overview of the firmware architecture. This work concludes by a brief investigation of switching waveforms of SiC MOSFETs acquired during the converter operation. Attention is called to a transistor current measurement with a low-cost current sensing resistor and its frequency characteristic compensation

Parametric analog signal amplification applied to nanoscale cmos wireless digital transceivers

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer Engineering by the Universidade Nova de Lisboa,Faculdade de Ciências e TecnologiaSignal amplification is required in almost every analog electronic system. However noise is also present, thus imposing limits to the overall circuit performance, e.g., on the sensitivity of the radio transceiver. This drawback has triggered a major research on the field, which has been producing several solutions to achieve amplification with minimum added noise. During the Fifties, an interesting out of mainstream path was followed which was based on variable reactance instead of resistance based amplifiers. The principle of these parametric circuits permits to achieve low noise amplifiers since the controlled variations of pure reactance elements is intrinsically noiseless. The amplification is based on a mixing effect which enables energy transfer from an AC pump source to other related signal frequencies. While the first implementations of these type of amplifiers were already available at that time, the discrete-time version only became visible more recently. This discrete-time version is a promising technique since it is well adapted to the mainstream nanoscale CMOS technology. The technique itself is based on the principle of changing the surface potential of the MOS device while maintaining the transistor gate in a floating state. In order words, the voltage amplification is achieved by changing the capacitance value while maintaining the total charge unchanged during an amplification phase. Since a parametric amplifier is not intrinsically dependent on the transconductance of the MOS transistor, it does not directly suffer from the intrinsic transconductance MOS gain issues verified in nanoscale MOS technologies. As a consequence, open-loop and opamp free structures can further emerge with this additional contribution. This thesis is dedicated to the analysis of parametric amplification with special emphasis on the MOS discrete-time implementation. The use of the latter is supported on the presentation of several circuits where the MOS Parametric Amplifier cell is well suited: small gain amplifier, comparator, discrete-time mixer and filter, and ADC. Relatively to the latter, a high speed time-interleaved pipeline ADC prototype is implemented in a,standard 130 nm CMOS digital technology from United Microelectronics Corporation (UMC). The ADC is fully based on parametric MOS amplification which means that one could achieve a compact and MOS-only implementation. Furthermore, any high speed opamp has not been used in the signal path, being all the amplification steps implemented with open-loop parametric MOS amplifiers. To the author’s knowledge, this is first reported pipeline ADC that extensively used the parametric amplification concept.Fundação para a Ciência e Tecnologia through the projects SPEED, LEADER and IMPAC