From Cleanroom to Desktop: Emerging Micro-Nanofabrication Technology for Biomedical Applications

This review is motivated by the growing demand for low-cost, easy-to-use, compact-size yet powerful micro-nanofabrication technology to address emerging challenges of fundamental biology and translational medicine in regular laboratory settings. Recent advancements in the field benefit considerably from rapidly expanding material selections, ranging from inorganics to organics and from nanoparticles to self-assembled molecules. Meanwhile a great number of novel methodologies, employing off-the-shelf consumer electronics, intriguing interfacial phenomena, bottom-up self-assembly principles, etc., have been implemented to transit micro-nanofabrication from a cleanroom environment to a desktop setup. Furthermore, the latest application of micro-nanofabrication to emerging biomedical research will be presented in detail, which includes point-of-care diagnostics, on-chip cell culture as well as bio-manipulation. While significant progresses have been made in the rapidly growing field, both apparent and unrevealed roadblocks will need to be addressed in the future. We conclude this review by offering our perspectives on the current technical challenges and future research opportunities

3D Integration, Temperature Effects, and Modeling

Practical limits to device scaling are threatening the growth of integrated circuit (IC) technology. A breakthrough architecture is needed in order to realize the increased device density and circuit functionality that future high performance ICs demand. 3D integration is being considered as this breakthrough architecture. In this thesis, the limits to scaling are noted and the feasibility of overcoming these limits using 3D integration is presented. The challenges and considerations, most notably dangerously high chip temperatures, are provided. To address the temperature concern, a mixed-mode simulator that calculates temperature as a function of position on chip is detailed. The simulator captures the important link between individual device and full chip heating. Lastly, circuit simulations and lab experiments are performed to experimentally validate the claims that differences in device activity on chip leads to dangerously high local and overall chip temperatures

Analog integrated circuit design in ultra-thin oxide CMOS technologies with significant direct tunneling-induced gate current

The ability to do mixed-signal IC design in a CMOS technology has been a driving force for manufacturing personal mobile electronic products such as cellular phones, digital audio players, and personal digital assistants. As CMOS has moved to ultra-thin oxide technologies, where oxide thicknesses are less than 3 nm, this type of design has been threatened by the direct tunneling of carriers though the gate oxide. This type of tunneling, which increases exponentially with decreasing oxide thickness, is a source of MOSFET gate current. Its existence invalidates the simplifying design assumption of infinite gate resistance. Its problems are typically avoided by switching to a high-&kappa/metal gate technology or by including a second thick(er) oxide transistor. Both of these solutions come with undesirable increases in cost due to extra mask and processing steps. Furthermore, digital circuit solutions to the problems created by direct tunneling are available, while analog circuit solutions are not. Therefore, it is desirable that analog circuit solutions exist that allow the design of mixed-signal circuits with ultra-thin oxide MOSFETs. This work presents a methodology that develops these solutions as a less costly alternative to high-&kappa/metal gate technologies or thick(er) oxide transistors. The solutions focus on transistor sizing, DC biasing, and the design of current mirrors and differential amplifiers. They attempt to minimize, balance, and cancel the negative effects of direct tunneling on analog design in traditional (non-high-&kappa/metal gate) ultra-thin oxide CMOS technologies. They require only ultra-thin oxide devices and are investigated in a 65 nm CMOS technology with a nominal VDD of 1 V and a physical oxide thickness of 1.25 nm. A sub-1 V bandgap voltage reference that requires only ultra-thin oxide MOSFETs is presented (TC = 251.0 ppm/°C). It utilizes the developed methodology and illustrates that it is capable of suppressing the negative effects of direct tunneling. Its performance is compared to a thick-oxide voltage reference as a means of demonstrating that ultra-thin oxide MOSFETs can be used to build the analog component of a mixed-signal system