Comparative Study of Various Systems on Chips Embedded in Mobile Devices

Systems-on-chips (SoCs) are the latest incarnation of very large scale integration (VLSI) technology. A single integrated circuit can contain over 100 million transistors. Harnessing all this computing power requires designers to move beyond logic design into computer architecture, meet real-time deadlines, ensure low-power operation, and so on. These opportunities and challenges make SoC design an important field of research. So in the paper we will try to focus on the various aspects of SOC and the applications offered by it. Also the different parameters to be checked for functional verification like integration and complexity are described in brief. We will focus mainly on the applications of system on chip in mobile devices and then we will compare various mobile vendors in terms of different parameters like cost, memory, features, weight, and battery life, audio and video applications. A brief discussion on the upcoming technologies in SoC used in smart phones as announced by Intel, Microsoft, Texas etc. is also taken up. Keywords: System on Chip, Core Frame Architecture, Arm Processors, Smartphone

Miniature and Low-Power Wireless Sensor Node Platform: State of the Art and Current Trends

Wireless sensor node is an autonomous and compact device that has capability to monitor a variety of real-world phenomena. It is designed composed of sensing device, embedded processor, communication module, and power equipment. Wireless sensor node is part of wireless sensor network where hundred or thousand sensor node can be deployed. Over the past decade Wireless Sensor Networks (WSNs) have emerged as one of the computing platforms of note within the electronics community. In prediction, there will be more than 127 million wireless sensor nodes deployed worldwide by 2014. We have surveyed 100 currently available wireless sensor network node platforms have been developed and produced not only by the research institutions, the universities but also some companies in last ten years. In this paper, we present a review of 27 different wireless sensor node platforms. We review these devices under a number of different parameters, and we highlight the key advantages of each node platform according to dimension and power consumption. We also discuss the characteristics and trend of development and deployment a wireless sensor node technology

ToSHI - Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance

The semiconductor industry is entering a new age in which device scaling and cost reduction will no longer follow the decades-long pattern. Packing more transistors on a monolithic IC at each node becomes more difficult and expensive. Companies in the semiconductor industry are increasingly seeking technological solutions to close the gap and enhance cost-performance while providing more functionality through integration. Putting all of the operations on a single chip (known as a system on a chip, or SoC) presents several issues, including increased prices and greater design complexity. Heterogeneous integration (HI), which uses advanced packaging technology to merge components that might be designed and manufactured independently using the best process technology, is an attractive alternative. However, although the industry is motivated to move towards HI, many design and security challenges must be addressed. This paper presents a three-tier security approach for secure heterogeneous integration by investigating supply chain security risks, threats, and vulnerabilities at the chiplet, interposer, and system-in-package levels. Furthermore, various possible trust validation methods and attack mitigation were proposed for every level of heterogeneous integration. Finally, we shared our vision as a roadmap toward developing security solutions for a secure heterogeneous integration

Analyse et caractérisation des couplages substrat et de la connectique dans les circuits 3D : Vers des modèles compacts

The 3D integration is the most promising technological solution to track the level of integration dictated by Moore's Law (see more than Moore, Moore versus more). It leads to important research for a dozen years. It can superimpose different circuits and components in one box. Its main advantage is to allow a combination of heterogeneous and highly specialized technologies for the establishment of a complete system, while maintaining a high level of performance with very short connections between the different circuits. The objective of this work is to provide consistent modeling via crossing, and / or contacts in the substrate, with various degrees of finesse / precision to allow the high-level designer to manage and especially to optimize the partitioning between the different strata. This modelization involves the development of multiple views at different levels of abstraction: the physical model to "high level" model. This would allow to address various issues faced in the design process: - The physical model using an electromagnetic simulation based on 2D or 3D ( finite element solver ) is used to optimize the via (materials, dimensions etc..) It determines the electrical performance of the via, including high frequency. Electromagnetic simulations also quantify the coupling between adjacent via. - The analytical compact of via their coupling model, based on a description of transmission line or Green cores is used for the simulations at the block level and Spice type simulations. Analytical models are often validated against measurements and / or physical models.L’intégration 3D est la solution technologique la plus prometteuse pour suivre le niveau d’intégration dictée par la loi de Moore (cf. more than Moore, versus more Moore). Elle entraine des travaux de recherche importants depuis une douzaine d’années. Elle permet de superposer différents circuits et composants dans un seul boitier. Son principal avantage est de permettre une association de technologies hétérogènes et très spécialisées pour la constitution d’un système complet, tout en préservant un très haut niveau de performance grâce à des connexions très courtes entre ces différents circuits. L’objectif de ce travail est de fournir des modélisations cohérentes de via traversant, ou/et de contacts dans le substrat, avec plusieurs degrés de finesse/précision, pour permettre au concepteur de haut niveau de gérer et surtout d’optimiser le partitionnement entre les différentes strates. Cette modélisation passe par le développement de plusieurs vues à différents niveaux d’abstraction: du modèle physique au modèle « haut niveau ». Elle devait permettre de répondre à différentes questions rencontrées dans le processus de conception :- le modèle physique de via basé sur une simulation électromagnétique 2D ou 3D (solveur « éléments finis ») est utilisé pour optimiser l’architecture du via (matériaux, dimensions etc.) Il permet de déterminer les performances électriques des via, notamment en haute fréquence. Les simulations électromagnétiques permettent également de quantifier le couplage entre via adjacents. - le modèle compact analytique de via et de leur couplage, basé sur une description de type ligne de transmission ou noyaux de Green, est utilisé pour les simulations au niveau bloc, ainsi que des simulations de type Spice. Les modèles analytiques sont souvent validés par rapport à des mesures et/ou des modèles physiques

Radiation Tolerant Electronics, Volume II

Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation hardened electronics for space applications, high-energy physics experiments such as those on the large hadron collider at CERN, and many terrestrial nuclear applications, including nuclear energy and safety management. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their ionizing radiation susceptibility has raised many exciting challenges, which are expected to drive research in the coming decade.After the success of the first Special Issue on Radiation Tolerant Electronics, the current Special Issue features thirteen articles highlighting recent breakthroughs in radiation tolerant integrated circuit design, fault tolerance in FPGAs, radiation effects in semiconductor materials and advanced IC technologies and modelling of radiation effects

Design, fabrication, and reliability study of second-level compliant microelectronic interconnects

Free-standing off-chip interconnects have high in-plane and out-of-plane compliance and are being pursued in academia and industry to reduce die stresses and to enhance interconnect reliability. The geometry of the compliant interconnect, its dimensions, and the material and processes used for fabricating the interconnect influence its mechanical and electrical characteristics, fabrication and assembly yield, thermo-mechanical and drop-impact reliability, and cost of fabrication. Although studies have examined various compliant interconnect designs, a multi-objective and multi-physics design optimization of the compliant interconnect has not been adequately pursued and implemented in prototypes. The first objective of this thesis is to develop a second-level multi-path compliant interconnect for microelectronic systems by performing compliance analysis and multi-physics design optimization using analytical and numerical models; The second objective of this thesis is to develop dry-film based sequential processes to fabricate such compliant interconnects on a silicon wafer, and to assemble singulated silicon substrates on organic printed circuit boards. In particular, in this work, the fabricated interconnects form a 45 × 45 array on the 18 mm × 18 mm silicon substrate. Several variations of the interconnects have been fabricated with the arcuate beam having a width of 10, 15, and 20µm on a footprint of 280µm, and with a pitch of 400µm. The third objective of this work is to experimentally demonstrate the thermal cycling reliability of the assemblies, and to validate the results from numerical models. The fourth objective is to experimentally demonstrate that compliant interconnects can effectively isolate the silicon substrate from the board under drop impact conditions, and to determine the reliability of the interconnects under drop impact conditions. It is seen that the compliant interconnects are able to isolate the silicon substrate from the board, and the board-to-substrate strain ratios are 21.55, 9.53 and 7.01 for compliant interconnects with arcuate beam width equal to 10μm, 15μm and 20μm, respectively, compared to 2.46 for solder ball interconnects. The experimental drop impact results are used for validating the drop-impact simulation predictions. Overall, by combining cleanroom fabrication, assembly, thermal cycling and drop-impact testing with analytical and numerical models as well as design optimization, this work provides a comprehensive insight into the development of multi-path copper structures as second-level microsystem interconnects.Ph.D

Memory Hierarchy Design for Next Generation Scalable Many-core Platforms

Performance and energy consumption in modern computing platforms is largely dominated by the memory hierarchy. The increasing computational power in the multiprocessors and accelerators, and the emergence of the data-intensive workloads (e.g. large-scale graph traversal and scientific algorithms) requiring fast transfer of large volumes of data, are two main trends which intensify this problem by putting even higher pressure on the memory hierarchy. This increasing gap between computation speed and data transfer speed is commonly referred as the “memory wall” problem. With the emergence of heterogeneous Three Dimensional (3D) Integration based on through-silicon-vias (TSV), this situation has started to recover in the past years. On one hand, it is now possible to improve memory access bandwidth and/or latency by either stacking memories directly on top of processors or through abstracted memory interfaces such as Micron’s Hybrid Memory Cube (HMC). On the other hand, near memory computation has become worthy of revisiting due to the cost-effective integration of logic and memory in 3D stacks. These two directions bring about several interesting opportunities including performance improvement, energy and cost reduction, product miniaturization, and modular design for improved time to market. In this research, we study the effectiveness of the 3D integration technology and the optimization opportunities which it can provide in the different layers of the memory hierarchy in cluster-based many-core platforms ranging from intra-cluster L1 to inter-cluster L2 scratchpad memories (SPMs), as well as the main memory. In addition, by moving a part of the computation to where data resides, in the 3D-stacked memory context, we demonstrate further energy and performance improvement opportunities