Static random-access memory designs based on different FinFET at lower technology node (7nm)

Title from PDF of title page viewed January 15, 2020Thesis advisor: Masud H ChowdhuryVitaIncludes bibliographical references (page 50-57)Thesis (M.S.)--School of Computing and Engineering. University of Missouri--Kansas City, 2019The Static Random-Access Memory (SRAM) has a significant performance impact on current nanoelectronics systems. To improve SRAM efficiency, it is important to utilize emerging technologies to overcome short-channel effects (SCE) of conventional CMOS. FinFET devices are promising emerging devices that can be utilized to improve the performance of SRAM designs at lower technology nodes. In this thesis, I present detail analysis of SRAM cells using different types of FinFET devices at 7nm technology. From the analysis, it can be concluded that the performance of both 6T and 8T SRAM designs are improved. 6T SRAM achieves a 44.97% improvement in the read energy compared to 8T SRAM. However, 6T SRAM write energy degraded by 3.16% compared to 8T SRAM. Read stability and write ability of SRAM cells are determined using Static Noise Margin and N- curve methods. Moreover, Monte Carlo simulations are performed on the SRAM cells to evaluate process variations. Simulations were done in HSPICE using 7nm Asymmetrical Underlap FinFET technology. The quasiplanar FinFET structure gained considerable attention because of the ease of the fabrication process [1] – [4]. Scaling of technology have degraded the performance of CMOS designs because of the short channel effects (SCEs) [5], [6]. Therefore, there has been upsurge in demand for FinFET devices for emerging market segments including artificial intelligence and cloud computing (AI) [8], [9], Internet of Things (IoT) [10] – [13] and biomedical [17] –[18] which have their own exclusive style of design. In recent years, many Underlapped FinFET devices were proposed to have better control of the SCEs in the sub-nanometer technologies [3], [4], [19] – [33]. Underlap on either side of the gate increases effective channel length as seen by the charge carriers. Consequently, the source-to-drain tunneling probability is improved. Moreover, edge direct tunneling leakage components can be reduced by controlling the electric field at the gate-drain junction . There is a limitation on the extent of underlap on drain or source sides because the ION is lower for larger underlap. Additionally, FinFET based designs have major width quantization issue. The width of a FinFET device increases only in quanta of silicon fin height (HFIN) [4]. The width quantization issue becomes critical for ratioed designs like SRAMs, where proper sizing of the transistors is essential for fault-free operation. FinFETs based on Design/Technology Co-Optimization (DTCO_F) approach can overcome these issues [38]. DTCO_F follows special design rules, which provides the specifications for the standard SRAM cells with special spacing rules and low leakages. The performances of 6T SRAM designs implemented by different FinFET devices are compared for different pull-up, pull down and pass gate transistor (PU: PD:PG) ratios to identify the best FinFET device for high speed and low power SRAM applications. Underlapped FinFETs (UF) and Design/Technology Co-Optimized FinFETs (DTCO_F) are used for the design and analysis. It is observed that with the PU: PD:PG ratios of 1:1:1 and 1:5:2 for the UF-SRAMs the read energy has degraded by 3.31% and 48.72% compared to the DTCO_F-SRAMs, respectively. However, the read energy with 2:5:2 ratio has improved by 32.71% in the UF-SRAM compared to the DTCO_F-SRAMs. The write energy with 1:1:1 configuration has improved by 642.27% in the UF-SRAM compared to the DTCO_F-SRAM. On the other hand, the write energy with 1:5:2 and 2:5:2 configurations have degraded by 86.26% and 96% in the UF-SRAMs compared to the DTCO_F-SRAMs. The stability and reliability of different SRAMs are also evaluated for 500mV supply. From the analysis, it can be concluded that Asymmetrical Underlapped FinFET is better for high-speed applications and DTCO FinFET for low power applications.Introduction -- Next generation high performance device: FinFET -- FinFET based SRAM bitcell designs -- Benchmarking of UF-SRAMs and DTCO-F-SRAMS -- Collaborative project -- Internship experience at INTEL and Marvell Semiconductor -- Conclusion and future wor

Nanosatellite fabrication and analysis

The advancements in technologies used in the aerospace industry have allowed universities to experiment with and develop small-scale satellites. Universities are taking advantage of the relatively low development costs of nanosatellite programs to give students experience in the field of spacecraft design. The purpose of Santa Clara University\u27s team, Nanosatellite Fabrication and Analysis, is to create a process to expedite the design, analysis, and fabrication phase of nanosatellite structures for students working on future satellite missions. The objective is to design four baseline nanosatellite structures to accommodate a range of potential missions where the designs are simple enough to be completely fabricated by students utilizing only the tools found in the Santa Clara University\u27s machine lab. Finite element analysis is conducted to ensure the designs meet NASA standards for natural frequency and that it can survive the forces it is subjected to during a launch. SatTherm, an easy to use thermal analysis tool for small spacecrafts, was used to conduct initial thermal simulations of the nanosatellite to determine the type of thermal components that will work for future missions. The success of team Nanosatellite Fabrication and Analysis proves that students can fabricate the structural frame of a nanosatellite using only the tools available in SCU\u27s machine lab

NFIRAOS First Facility AO System for the Thirty Meter Telescope

NFIRAOS, the Thirty Meter Telescope's first adaptive optics system is an order 60x60 Multi-Conjugate AO system with two deformable mirrors. Although most observing will use 6 laser guide stars, it also has an NGS-only mode. Uniquely, NFIRAOS is cooled to -30 C to reduce thermal background. NFIRAOS delivers a 2-arcminute beam to three client instruments, and relies on up to three IR WFSs in each instrument. We present recent work including: robust automated acquisition on these IR WFSs; trade-off studies for a common-size of deformable mirror; real-time computing architectures; simplified designs for high-order NGS-mode wavefront sensing; modest upgrade concepts for high-contrast imaging.Comment: ..submitted to SPIE 9148 Astronomical Telescopes and Instrumentation - Adaptive Optics Systems IV (2014

Comprehensive Mapping and Benchmarking of Esaki Diode Performance

The tunneling-FET (TFET) has been identified as a prospective MOSFET replacement technology with the potential to extend geometric and electrostatic scaling of digital integrated circuits. However, experimental demonstrations of the TFET have yet to reliably achieve drive currents necessary to power large scale integrated circuits. Consequentially, much effort has gone into optimizing the band-to-band tunneling (BTBT) efficiency of the TFET. In this work, the Esaki tunnel diode (ETD) is used as a short loop element to map and optimize BTBT performance for a large design space. The experimental results and tools developed for this work may be used to (1) map additional and more complicated ETD structures, (2) guide development of improved TFET structures and BTBT devices, (3) design ETDs targeted BTBT characteristics, and (4) calibrate BTBT models. The first objective was to verify the quality of monolithically integrated III-V based ETDs on Si substrates (the industry standard). Five separate GaAs/InGaAs ETDs were fabricated on GaAs-virtual substrates via aspect ratio trapping, along with two companion ETDs grown on Si and GaAs bulk substrates. The quality of the virtual substrates and BTBT were verified with (i) very large peak-valley current ratios (up to 56), (ii) temperature measurements, and (iii) deep sub-micron scaling. The second objective mapped the BTBT characteristics of the In1-xGaxAs ternary system by (1) standardizing the ETD structure, (2) limiting experimental work to unstrained (i) GaAs, (ii) In0.53Ga0.47As, and (iii) InAs homojunctions, and (3) systematically varying doping concentrations. Characteristic BTBT trendlines were determined for each material system, ranging from ultra-low to ultra-high peak current densities (JP) of 11 μA/cm2 to 975 kA/cm2 for GaAs and In0.53Ga0.47As, respectively. Furthermore, the BTBT mapping results establishes that BTBT current densities can only be improved by ~2-3 times the current record, by increasing doping concentration and In content up to ~75%. The E. O. Kane BTBT model has been shown to accurately predict the tunneling characteristics for the entire design space. Furthermore, it was used to help guide the development of a new universal BTBT model, which is a closed form exponential using 2 fitting parameters, material constants, and doping concentrations. With it, JP can quickly be predicted over the entire design space of this work

Automatic Romaine Heart Harvester

The Romaine Robotics Senior Design Team developed a romaine lettuce heart trimming system in partnership with a Salinas farm to address a growing labor shortage in the agricultural industry that is resulting in crops rotting in the field before they could be harvested. An automated trimmer can alleviate the most time consuming step in the cut-trim-bag harvesting process, increasing the yields of robotic cutters or the speed of existing laborer teams. Leveraging the Partner Farm’s existing trimmer architecture, which consists of a laborer loading lettuce into sprungloaded grippers that are rotated through vision and cutting systems by an indexer, the team redesigned geometry to improve the loading, gripping, and ejection stages of the system. Physical testing, hand calculations, and FEA were performed to understand acceptable grip strengths and cup design, and several wooden mockups were built to explore a new actuating linkage design for the indexer. The team manufactured, assembled, and performed verification testing on a full-size metal motorized prototype that can be incorporated with the Partner Farm’s existing cutting and vision systems. The prototype met all of the established requirements, and the farm has implemented the redesign onto their trimmer. Future work would include designing and implementing vision and cutting systems for the team’s metal prototype

Computing SpMV on FPGAs

There are hundreds of papers on accelerating sparse matrix vector multiplication (SpMV), however, only a handful target FPGAs. Some claim that FPGAs inherently perform inferiorly to CPUs and GPUs. FPGAs do perform inferiorly for some applications like matrix-matrix multiplication and matrix-vector multiplication. CPUs and GPUs have too much memory bandwidth and too much floating point computation power for FPGAs to compete. However, the low computations to memory operations ratio and irregular memory access of SpMV trips up both CPUs and GPUs. We see this as a leveling of the playing field for FPGAs. Our implementation focuses on three pillars: matrix traversal, multiply-accumulator design, and matrix compression. First, most SpMV implementations traverse the matrix in row-major order, but we mix column and row traversal. Second, To accommodate the new traversal the multiply accumulator stores many intermediate y values. Third, we compress the matrix to increase the transfer rate of the matrix from RAM to the FPGA. Together these pillars enable our SpMV implementation to perform competitively with CPUs and GPUs

Model-guided Design of RNA-based Synthetic Circuits for the Dynamic Regulation of Gene Expression

A longstanding goal in synthetic biology has been to build synthetic gene circuits with the ability to harness nature’s capability of precise gene expression regulation. Advancements in RNA technology have established RNA-based regulators with distinct advantages over traditional protein-based regulators such as faster signal propagation, versatile programmability, and low cellular burden, which has created an interest in the field to construct innovative synthetic gene circuits using de novo RNA- based regulators. However, our understanding of the behavior and kinetics of RNA-RNA interactions for the construction of gene circuits is incomplete. This thesis proposes a model-guided design framework that integrates mechanistic modeling and statistical analysis with experimental efforts to overcome this challenge. The proposed framework features: first, define the application of gene circuit; second, select the circuit\u27s architecture and relevant gene regulatory components based on desired dynamics; third, develop a mathematical model to describe the involved biomolecular reaction in the system and identify relevant kinetic information from literature; fourth, perform in vivo or in vitro experimental construction and validation of the circuit. The feasibility of the framework is first demonstrated by assessing the viability of an RNA-only I1-FFL gene circuit. The proposed design is evaluated using a combined experimental and mathematical approach to elucidate the kinetics of RNA-RNA interactions for timescale critical circuit architectures. The framework is then extended to evaluate the relationship between regulation level (transcription or translation) and circuit dynamics using four design variations of the I1-FFL circuit. The performance of each circuit is compared using mechanistic modeling, statistical analysis, and standard control theory concepts, which provide a quantitative way to reveal the effect of regulation level and circuit behavior. The major contributions of this thesis include: (1) it demonstrates the utility of modeling to troubleshoot and debug circuit design (2) it reveals the importance of regulation level in designing synthetic circuits. Together, the findings presented in this thesis aim to facilitate the design and implementation of gene circuits with increased complexity and functionality