Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique

[[abstract]]This brief describes an ultralow-voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultralow voltage. The chip is fabricated in a 0.13-mum standard CMOS process with a 0.5-V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610 MHz with a 0.5-V power supply voltage. At 550 MHz, the measured root-mean-square jitter and peak-to-peak jitter are 8.01 and 56.36 ps, respectively. The total power consumption of the PLL is 1.25 mW, and the active die area of the PLL is 0.04 mm2.[[notice]]補正完畢[[incitationindex]]SCI[[incitationindex]]EI[[booktype]]紙

Low-Voltage Ultra-Low-Power Current Conveyor Based on Quasi-Floating Gate Transistors

The field of low-voltage low-power CMOS technology has grown rapidly in recent years; it is an essential prerequisite particularly for portable electronic equipment and implantable medical devices due to its influence on battery lifetime. Recently, significant improvements in implementing circuits working in the low-voltage low-power area have been achieved, but circuit designers face severe challenges when trying to improve or even maintain the circuit performance with reduced supply voltage. In this paper, a low-voltage ultra-low-power current conveyor second generation CCII based on quasi-floating gate transistors is presented. The proposed circuit operates at a very low supply voltage of only ±0.4 V with rail-to-rail voltage swing capability and a total quiescent power consumption of mere 9.5 µW. Further, the proposed circuit is not only able to process the AC signal as it's usual at quasi-floating gate transistors but also the DC which extends the applicability of the proposed circuit. In conclusion, an application example of the current-mode quadrature oscillator is presented. PSpice simulation results using the 0.18 µm TSMC CMOS technology are included to confirm the attractive properties of the proposed circuit

CMOS analog integrated circuit design techniques for low-powered ubiquitous device

制度:新 ; 文部省報告番号:甲2633号 ; 学位の種類:博士(工学) ; 授与年月日:2008/3/15 ; 早大学位記番号:新479

Low Voltage Low Power Analogue Circuits Design

Disertační práce je zaměřena na výzkum nejběžnějších metod, které se využívají při návrhu analogových obvodů s využití nízkonapěťových (LV) a nízkopříkonových (LP) struktur. Tyto LV LP obvody mohou být vytvořeny díky vyspělým technologiím nebo také využitím pokročilých technik návrhu. Disertační práce se zabývá právě pokročilými technikami návrhu, především pak nekonvenčními. Mezi tyto techniky patří využití prvků s řízeným substrátem (bulk-driven - BD), s plovoucím hradlem (floating-gate - FG), s kvazi plovoucím hradlem (quasi-floating-gate - QFG), s řízeným substrátem s plovoucím hradlem (bulk-driven floating-gate - BD-FG) a s řízeným substrátem s kvazi plovoucím hradlem (quasi-floating-gate - BD-QFG). Práce je také orientována na možné způsoby implementace známých a moderních aktivních prvků pracujících v napěťovém, proudovém nebo mix-módu. Mezi tyto prvky lze začlenit zesilovače typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za účelem potvrzení funkčnosti a chování výše zmíněných struktur a prvků byly vytvořeny příklady aplikací, které simulují usměrňovací a induktanční vlastnosti diody, dále pak filtry dolní propusti, pásmové propusti a také univerzální filtry. Všechny aktivní prvky a příklady aplikací byly ověřeny pomocí PSpice simulací s využitím parametrů technologie 0,18 m TSMC CMOS. Pro ilustraci přesného a účinného chování struktur je v disertační práci zahrnuto velké množství simulačních výsledků.The dissertation thesis is aiming at examining the most common methods adopted by analog circuits' designers in order to achieve low voltage (LV) low power (LP) configurations. The capability of LV LP operation could be achieved either by developed technologies or by design techniques. The thesis is concentrating upon design techniques, especially the non–conventional ones which are bulk–driven (BD), floating–gate (FG), quasi–floating–gate (QFG), bulk–driven floating–gate (BD–FG) and bulk–driven quasi–floating–gate (BD–QFG) techniques. The thesis also looks at ways of implementing structures of well–known and modern active elements operating in voltage–, current–, and mixed–mode such as operational transconductance amplifier (OTA), second generation current conveyor (CCII), fully–differential second generation current conveyor (FB–CCII), fully–balanced differential difference amplifier (FB–DDA), voltage differencing transconductance amplifier (VDTA), current–controlled current differencing buffered amplifier (CC–CDBA) and current feedback operational amplifier (CFOA). In order to confirm the functionality and behavior of these configurations and elements, they have been utilized in application examples such as diode–less rectifier and inductance simulations, as well as low–pass, band–pass and universal filters. All active elements and application examples have been verified by PSpice simulator using the 0.18 m TSMC CMOS parameters. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of structures.

Nanomechanical Resonators: Toward Atomic Scale

The quest for realizing and manipulating ever smaller man-made movable structures and dynamical machines has spurred tremendous endeavors, led to important discoveries, and inspired researchers to venture to new grounds. Scientific feats and technological milestones of miniaturization of mechanical structures have been widely accomplished by advances in machining and sculpturing ever shrinking features out of bulk materials such as silicon. With the flourishing multidisciplinary field of low-dimensional nanomaterials, including one-dimensional (1D) nanowires/nanotubes, and two-dimensional (2D) atomic layers such as graphene/phosphorene, growing interests and sustained efforts have been devoted to creating mechanical devices toward the ultimate limit of miniaturization— genuinely down to the molecular or even atomic scale. These ultrasmall movable structures, particularly nanomechanical resonators that exploit the vibratory motion in these 1D and 2D nano-to-atomic-scale structures, offer exceptional device-level attributes, such as ultralow mass, ultrawide frequency tuning range, broad dynamic range, and ultralow power consumption, thus holding strong promises for both fundamental studies and engineering applications. In this Review, we offer a comprehensive overview and summary of this vibrant field, present the state-of-the-art devices and evaluate their specifications and performance, outline important achievements, and postulate future directions for studying these miniscule yet intriguing molecular-scale machines

Lithium niobate RF-MEMS oscillators for IoT, 5G and beyond

This dissertation focuses on the design and implementation of lithium niobate (LiNbO3) radiofrequency microelectromechanical (RF-MEMS) oscillators for internet-of-things (IoT), 5G and beyond. The dissertation focuses on solving two main problems found nowadays in most of the published works: the narrow tuning range and the low operating frequency (sub 3 GHz) acoustic oscillators currently deliver. The work introduced here enables wideband voltage-controlled MEMS oscillators (VCMOs) needed for emerging applications in IoT. Moreover, it enables multi-GHz (above 8 GHz) RF-MEMS oscillators through harnessing over mode resonances for 5G and beyond. LiNbO3 resonators characterized by high-quality factor (Q), high electromechanical coupling (kt2), and high figure-of-merit (FoMRES= Q kt2) are crucial for building the envisioned high-performance oscillators. Those oscillators can be enabled with lower power consumption, wider tuning ranges, and a higher frequency of oscillation when compared to other state-of-the-art (SoA) RF-MEMS oscillators. Tackling the tuning range issue, the first VCMO based on the heterogeneous integration of a high Q LiNbO3 RF-MEMS resonator and complementary metal-oxide semiconductor (CMOS) is demonstrated in this dissertation. A LiNbO3 resonator array with a series resonance of 171.1 MHz, a Q of 410, and a kt2 of 12.7% is adopted, while the TSMC 65 nm RF LP CMOS technology is used to implement the active circuitry with an active area of 220×70 µm2. Frequency tuning of the VCMO is achieved by programming a binary-weighted digital capacitor bank and a varactor that are both connected in series to the resonator. The measured best phase noise performances of the VCMO are -72 and -153 dBc/Hz at 1 kHz and 10 MHz offsets from 178.23 and 175.83 MHz carriers, respectively. The VCMO consumes a direct current (DC) of 60 µA from a 1.2 V supply while realizing a tuning range of 2.4 MHz (~ 1.4% tuning range). Such VCMOs can be applied to enable ultralow-power, low phase noise, and wideband RF synthesis for emerging applications in IoT. Moreover, the first VCMO based on LiNbO3 lateral overtone bulk acoustic resonator (LOBAR) is demonstrated in this dissertation. The LOBAR excites over 30 resonant modes in the range of 100 to 800 MHz with a frequency spacing of 20 MHz. The VCMO consists of a LOBAR in a closed-loop with two amplification stages and a varactor-embedded tunable LC tank. By the bias voltage applied to the varactor, the tank can be tuned to change the closed-loop gain and phase responses of the oscillator so that Barkhausen’s conditions are satisfied for the targeted resonant mode. The tank is designed to allow the proposed VCMO to lock to any of the ten overtones ranging from 300 to 500 MHz. These ten tones are characterized by average Qs of 2100, kt2 of 1.5%, FoMRES of 31.5 enabling low phase noise, and low-power oscillators crucial for IoT. Owing to the high Qs of the LiNbO3 LOBAR, the measured VCMO shows a close-in phase noise of -100 dBc/Hz at 1 kHz offset from a 300 MHz carrier and a noise floor of -153 dBc/Hz while consuming 9 mW. With further optimization, this VCMO can lead to direct RF synthesis for ultra-low-power transceivers in multi-mode IoT nodes. Tackling the multi-GHz operation problem, the first Ku-band RF-MEMS oscillator utilizing a third antisymmetric overtone (A3) in a LiNbO3 resonator is presented in the dissertation. Quarter-wave resonators are used to satisfy Barkhausen’s oscillation conditions for the 3rd overtone while suppressing the fundamental and higher-order resonances. The oscillator achieves measured phase noise of -70 and -111 dBc/Hz at 1 kHz and 100 kHz offsets from a 12.9 GHz carrier while consuming 20 mW of dc power. The oscillator achieves a FoMOSC of 200 dB at 100 kHz offset. The achieved oscillation frequency is the highest reported to date for a MEMS oscillator. In addition, this dissertation introduces the first X-band RF-MEMS oscillator built using CMOS technology. The oscillator consists of an acoustic resonator in a closed loop with cascaded RF tuned amplifiers (TAs) built on TSMC RF GP 65 nm CMOS. The TAs bandpass response, set by on-chip inductors, satisfies Barkhausen's oscillation conditions for A3 only. Two circuit variations are implemented. The first is an 8.6 GHz standalone oscillator with a source-follower buffer for direct 50 Ω-based measurements. The second is an oscillator-divider chain using an on-chip 3-stage divide-by-2 frequency divider for a ~1.1 GHz output. The standalone oscillator achieves measured phase noise of -56, -113, and -135 dBc/Hz at 1 kHz, 100 kHz, and 1 MHz offsets from an 8.6 GHz output while consuming 10.2 mW of dc power. The oscillator also attains a FoMOSC of 201.6 dB at 100 kHz offset, surpassing the SoA electromagnetic (EM) and RF-MEMS based oscillators. The oscillator-divider chain produces a phase noise of -69.4 and -147 dBc/Hz at 1 kHz and 1 MHz offsets from a 1075 MHz output while consuming 12 mW of dc power. Its phase noise performance also surpasses the SoA L-band phase-locked loops (PLLs). The demonstrated performance shows the strong potential of microwave acoustic oscillators for 5G frequency synthesis and beyond. This work will enable low-power 5G transceivers featuring high speed, high sensitivity, and high selectivity in small form factors

Ultra-Low-Power Sensors and Receivers for IoT Applications

The combination of ultra-low power analog front-ends and CMOS-compatible transducers enable new applications, such as environmental monitors, household appliances, health trackers, etc. that are seamlessly integrated into our daily lives. Furthermore, wireless connectivity allows many of these sensors to operate both independently and collectively. These techniques collectively fulfil the recent surge of internet-of-things (IoT) applications that have the potential to fundamentally change daily life for millions of people.In this dissertation, the circuit and system design of wireless receivers and sensors is presented that explores the challenges of implementing long lifespan, high accuracy, and large coverage range IoT sensor networks. The first is a wake-up receiver (WuRX), which continuously monitors the RF environment to wake up a higher-power radio upon detection of a predetermined RF signature. This work both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator.Although pushing the prior WuRX performance boundary by orders of magnitude, the first work shows moderate sensitivity, inferior temperature robustness, and large area with external lumped components. Thus, the second work shows a miniaturized WuRX that is temperature-compensated, yet still consumes only nano-watt power and millimeter area while operating at 9 GHz. To further reduce the area, a global common-mode feedback is utilized across the envelope detector and baseband amplifier that eliminates the need for off-chip ac-coupling components. Multiple temperature-compensation techniques are proposed to maintain constant bandwidth of the signal path and constant clock frequency. Both WuRXs operate at 0.4 V supply, consume near-zero power and achieve ~-70 dBm sensitivity.Lastly, the first reported CMOS 2-in-1 relative humidity and temperature sensor is presented. A unified analog front-end interfaces on-chip transducers and converts the inputs into a frequency vis a high-linearity frequency-locked loop. An incomplete-settling switched-capacitor-based Wheatstone bridge is proposed to sense the inputs in a power-efficient fashion

RF MEMS reference oscillators platform for wireless communications

A complete platform for RF MEMS reference oscillator is built to replace bulky quartz from mobile devices, thus reducing size and cost. The design targets LTE transceivers. A low phase noise 76.8 MHz reference oscillator is designed using material temperature compensated AlN-on-silicon resonator. The thesis proposes a system combining piezoelectric resonator with low loading CMOS cross coupled series resonance oscillator to reach state-of-the-art LTE phase noise specifications. The designed resonator is a two port fundamental width extensional mode resonator. The resonator characterized by high unloaded quality factor in vacuum is designed with low temperature coefficient of frequency (TCF) using as compensation material which enhances the TCF from - 3000 ppm to 105 ppm across temperature ranges of -40˚C to 85˚C. By using a series resonant CMOS oscillator, phase noise of -123 dBc/Hz at 1 kHz, and -162 dBc/Hz at 1MHz offset is achieved. The oscillator’s integrated RMS jitter is 106 fs (10 kHz–20 MHz), consuming 850 μA, with startup time is 250μs, achieving a Figure-of-merit (FOM) of 216 dB. Electronic frequency compensation is presented to further enhance the frequency stability of the oscillator. Initial frequency offset of 8000 ppm and temperature drift errors are combined and further addressed electronically. A simple digital compensation circuitry generates a compensation word as an input to 21 bit MASH 1 -1-1 sigma delta modulator incorporated in RF LTE fractional N-PLL for frequency compensation. Temperature is sensed using low power BJT band-gap front end circuitry with 12 bit temperature to digital converter characterized by a resolution of 0.075˚C. The smart temperature sensor consumes only 4.6 μA. 700 MHz band LTE signal proved to have the stringent phase noise and frequency resolution specifications among all LTE bands. For this band, the achieved jitter value is 1.29 ps and the output frequency stability is 0.5 ppm over temperature ranges from -40˚C to 85˚C. The system is built on 32nm CMOS technology using 1.8V IO device