694 research outputs found
Self-timed design in GaAs - case study of a high-speed parallel multiplier
Journal ArticleAbstract-The problems with synchronous designs at high clock frequencies have been well documented. This makes an asynchronous approach attractive for high speed technologies like GaAs. We investigate the issues involved by describing the design of a parallel multiplier that can be part of a floating point multiplier. We first present a new architecture called the partial army of array (PAA) that is more regular than a partial tree approach while having the same latency. We then show how this architecture can be used in a self-timed implementation in the style of micropipelines. We next describe how we can design the final carry propagate adder using a new precharged logic family in GaAs that we developed as part of this project. We conclude with some genera1 observations on doing asynchronous design in GaAs
A Breakdown Voltage Multiplier for High Voltage Swing Drivers
A novel breakdown voltage (BV) multiplier is introduced that makes it possible to generate high output voltage swings using transistors with low breakdown voltages. The timing analysis of the stage is used to optimize its dynamic response. A 10 Gb/s optical modulator driver with a differential output voltage swing of 8 V on a 50 Ω load was implemented in a SiGe BiCMOS process. It uses the BV-Doubler topology to achieve output swings twice the collector–emitter breakdown voltage without stressing any single transistor
DFT algorithms for bit-serial GaAs array processor architectures
Systems and Processes Engineering Corporation (SPEC) has developed an innovative array processor architecture for computing Fourier transforms and other commonly used signal processing algorithms. This architecture is designed to extract the highest possible array performance from state-of-the-art GaAs technology. SPEC's architectural design includes a high performance RISC processor implemented in GaAs, along with a Floating Point Coprocessor and a unique Array Communications Coprocessor, also implemented in GaAs technology. Together, these data processors represent the latest in technology, both from an architectural and implementation viewpoint. SPEC has examined numerous algorithms and parallel processing architectures to determine the optimum array processor architecture. SPEC has developed an array processor architecture with integral communications ability to provide maximum node connectivity. The Array Communications Coprocessor embeds communications operations directly in the core of the processor architecture. A Floating Point Coprocessor architecture has been defined that utilizes Bit-Serial arithmetic units, operating at very high frequency, to perform floating point operations. These Bit-Serial devices reduce the device integration level and complexity to a level compatible with state-of-the-art GaAs device technology
Wide-bandwidth high-resolution search for extraterrestrial intelligence
Research accomplished during the third 6-month period is summarized. Research covered the following: dual-horn antenna performance; high electron mobility transistors (HEMT) low-noise amplifiers; downconverters; fast Fourier transform (FFT) array; and backend 'feature recognizer' array
Gallium arsenide design methodology and testing of a systolic floating point processing element
Thesis (M.E.Sc.) -- University of Adelaide, Dept. of Electrical and Electronic Engineering, 199
Using FPGAs to prototype a self-timed floating point co-processor
Journal ArticleSelf- timed circuits offer advantages over their synchronously clocked counterparts in a number of situations. However, self-timed design techniques are not widely used at present for a variety of reasons. One reason for the lack of experimentation with self-timed systems is the lack of commercially available parts to support this style of design. Field programmable gate arrays (FPGAs) offer an excellent alternative for the rapid development of novel system designs provided suitable circuit structures can be implemented. This paper describes a self-timed floating point co-processor built using a combination of Actel Field Programmable Gate Arrays (FPGAs) and semi-custom CMOS chips. This co-processor implements IEEE standard single precision floating point operations on 32-bit values. The control is completely self-timed. Data moves between parts of the circuit according to local constraints only: there is no global clock or global control circuit
Second year technical report on-board processing for future satellite communications systems
Advanced baseband and microwave switching techniques for large domestic communications satellites operating in the 30/20 GHz frequency bands are discussed. The nominal baseband processor throughput is one million packets per second (1.6 Gb/s) from one thousand T1 carrier rate customer premises terminals. A frequency reuse factor of sixteen is assumed by using 16 spot antenna beams with the same 100 MHz bandwidth per beam and a modulation with a one b/s per Hz bandwidth efficiency. Eight of the beams are fixed on major metropolitan areas and eight are scanning beams which periodically cover the remainder of the U.S. under dynamic control. User signals are regenerated (demodulated/remodulated) and message packages are reformatted on board. Frequency division multiple access and time division multiplex are employed on the uplinks and downlinks, respectively, for terminals within the coverage area and dwell interval of a scanning beam. Link establishment and packet routing protocols are defined. Also described is a detailed design of a separate 100 x 100 microwave switch capable of handling nonregenerated signals occupying the remaining 2.4 GHz bandwidth with 60 dB of isolation, at an estimated weight and power consumption of approximately 400 kg and 100 W, respectively
The 1992 4th NASA SERC Symposium on VLSI Design
Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design
Computers for Lattice Field Theories
Parallel computers dedicated to lattice field theories are reviewed with
emphasis on the three recent projects, the Teraflops project in the US, the
CP-PACS project in Japan and the 0.5-Teraflops project in the US. Some new
commercial parallel computers are also discussed. Recent development of
semiconductor technologies is briefly surveyed in relation to possible
approaches toward Teraflops computers.Comment: 15 pages with 16 PS figures, review presented at Lattice 93, LaTeX
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