1,048 research outputs found
ENHANCEMENT OF MARKOV RANDOM FIELD MECHANISM TO ACHIEVE FAULT-TOLERANCE IN NANOSCALE CIRCUIT DESIGN
As the MOSFET dimensions scale down towards nanoscale level, the reliability of
circuits based on these devices decreases. Hence, designing reliable systems using
these nano-devices is becoming challenging. Therefore, a mechanism has to be
devised that can make the nanoscale systems perform reliably using unreliable circuit
components. The solution is fault-tolerant circuit design. Markov Random Field
(MRF) is an effective approach that achieves fault-tolerance in integrated circuit
design. The previous research on this technique suffers from limitations at the design,
simulation and implementation levels. As improvements, the MRF fault-tolerance
rules have been validated for a practical circuit example. The simulation framework is
extended from thermal to a combination of thermal and random telegraph signal
(RTS) noise sources to provide a more rigorous noise environment for the simulation
of circuits build on nanoscale technologies. Moreover, an architecture-level
improvement has been proposed in the design of previous MRF gates. The redesigned
MRF is termed as Improved-MRF.
The CMOS, MRF and Improved-MRF designs were simulated under application
of highly noisy inputs. On the basis of simulations conducted for several test circuits,
it is found that Improved-MRF circuits are 400 whereas MRF circuits are only 10
times more noise-tolerant than the CMOS alternatives. The number of transistors, on
the other hand increased from a factor of 9 to 15 from MRF to Improved-MRF
respectively (as compared to the CMOS). Therefore, in order to provide a trade-off
between reliability and the area overhead required for obtaining a fault-tolerant
circuit, a novel parameter called as ‘Reliable Area Index’ (RAI) is introduced in this
research work. The value of RAI exceeds around 1.3 and 40 times for MRF and
Improved-MRF respectively as compared to CMOS design which makes Improved-
MRF to be still 30 times more efficient circuit design than MRF in terms of
maintaining a suitable trade-off between reliability and area-consumption of the
circuit
Stochastic Digital Circuits for Probabilistic Inference
We introduce combinational stochastic logic, an abstraction that generalizes deterministic digital circuit design (based on Boolean logic gates) to the probabilistic setting. We show how this logic can be combined with techniques from contemporary digital design to generate stateless and stateful circuits for exact and approximate sampling from a range of probability distributions. We focus on Markov chain Monte Carlo algorithms for Markov random fields, using massively parallel circuits. We implement these circuits on commodity reconfigurable logic and estimate the resulting performance in time, space and price. Using our approach, these simple and general algorithms could be affordably run for thousands of iterations on models with hundreds of thousands of variables in real time
ENHANCEMENT OF MARKOV RANDOM FIELD MECHANISM TO ACHIEVE FAULT-TOLERANCE IN NANOSCALE CIRCUIT DESIGN
As the MOSFET dimensions scale down towards nanoscale level, the reliability of
circuits based on these devices decreases. Hence, designing reliable systems using
these nano-devices is becoming challenging. Therefore, a mechanism has to be
devised that can make the nanoscale systems perform reliably using unreliable circuit
components. The solution is fault-tolerant circuit design. Markov Random Field
(MRF) is an effective approach that achieves fault-tolerance in integrated circuit
design. The previous research on this technique suffers from limitations at the design,
simulation and implementation levels. As improvements, the MRF fault-tolerance
rules have been validated for a practical circuit example. The simulation framework is
extended from thermal to a combination of thermal and random telegraph signal
(RTS) noise sources to provide a more rigorous noise environment for the simulation
of circuits build on nanoscale technologies. Moreover, an architecture-level
improvement has been proposed in the design of previous MRF gates. The redesigned
MRF is termed as Improved-MRF.
The CMOS, MRF and Improved-MRF designs were simulated under application
of highly noisy inputs. On the basis of simulations conducted for several test circuits,
it is found that Improved-MRF circuits are 400 whereas MRF circuits are only 10
times more noise-tolerant than the CMOS alternatives. The number of transistors, on
the other hand increased from a factor of 9 to 15 from MRF to Improved-MRF
respectively (as compared to the CMOS). Therefore, in order to provide a trade-off
between reliability and the area overhead required for obtaining a fault-tolerant
circuit, a novel parameter called as ‘Reliable Area Index’ (RAI) is introduced in this
research work. The value of RAI exceeds around 1.3 and 40 times for MRF and
Improved-MRF respectively as compared to CMOS design which makes Improved-
MRF to be still 30 times more efficient circuit design than MRF in terms of
maintaining a suitable trade-off between reliability and area-consumption of the
circuit
A STUDY OF MRF CMOS CIRCUIT DESIGN IMPLEMENTATION
Shrinking devices to the smaller scale and reducing of voltage levels down to the
thermal limit, all conspire to produce faulty systems. One possible solution for this
matter is to have a paradigm shift to a fault tolerant probabilistic framework.
Probabilistic computing provides a new approach towards building fault-tolerant
architectures and systems. The logic states are considered to be random variables.
Under this framework, one no longer expects a correct logic signal at all nodes at all
times, but only that the joint probability distribution of signal values has the highest
likelihood for valid logic states. The probabilistic approach is based on the theory of
Markov Random Fields (MRF), which is extensible to a large number of logic
variables. This theory can be used to design the circuit with high noise immunity.
This report discusses about the inverter circuits, and comparison between the
obtained results for both MRF and Standard inverters using Cadence tools and
MA TLAB in both noisy and ideal conditions. The results are in micro-regime, since
the minimum dimensions of the software were in micro-ranges.
The project focused more on the analysis of noise for both inverters and the
transistors inside each one of them. As a result of completing the above procedure, it
was proved that MRF inverter is tolerant to noisy conditions where as the standard
inverter is not
Quick and energy-efficient Bayesian computing of binocular disparity using stochastic digital signals
Reconstruction of the tridimensional geometry of a visual scene using the
binocular disparity information is an important issue in computer vision and
mobile robotics, which can be formulated as a Bayesian inference problem.
However, computation of the full disparity distribution with an advanced
Bayesian model is usually an intractable problem, and proves computationally
challenging even with a simple model. In this paper, we show how probabilistic
hardware using distributed memory and alternate representation of data as
stochastic bitstreams can solve that problem with high performance and energy
efficiency. We put forward a way to express discrete probability distributions
using stochastic data representations and perform Bayesian fusion using those
representations, and show how that approach can be applied to diparity
computation. We evaluate the system using a simulated stochastic implementation
and discuss possible hardware implementations of such architectures and their
potential for sensorimotor processing and robotics.Comment: Preprint of article submitted for publication in International
Journal of Approximate Reasoning and accepted pending minor revision
Memory and information processing in neuromorphic systems
A striking difference between brain-inspired neuromorphic processors and
current von Neumann processors architectures is the way in which memory and
processing is organized. As Information and Communication Technologies continue
to address the need for increased computational power through the increase of
cores within a digital processor, neuromorphic engineers and scientists can
complement this need by building processor architectures where memory is
distributed with the processing. In this paper we present a survey of
brain-inspired processor architectures that support models of cortical networks
and deep neural networks. These architectures range from serial clocked
implementations of multi-neuron systems to massively parallel asynchronous ones
and from purely digital systems to mixed analog/digital systems which implement
more biological-like models of neurons and synapses together with a suite of
adaptation and learning mechanisms analogous to the ones found in biological
nervous systems. We describe the advantages of the different approaches being
pursued and present the challenges that need to be addressed for building
artificial neural processing systems that can display the richness of behaviors
seen in biological systems.Comment: Submitted to Proceedings of IEEE, review of recently proposed
neuromorphic computing platforms and system
Self-Healing Cellular Automata to Correct Soft Errors in Defective Embedded Program Memories
Static Random Access Memory (SRAM) cells in ultra-low power Integrated Circuits (ICs) based on nanoscale Complementary Metal Oxide Semiconductor (CMOS) devices are likely to be the most vulnerable to large-scale soft errors. Conventional error correction circuits may not be able to handle the distributed nature of such errors and are susceptible to soft errors themselves. In this thesis, a distributed error correction circuit called Self-Healing Cellular Automata (SHCA) that can repair itself is presented. A possible way to deploy a SHCA in a system of SRAM-based embedded program memories (ePM) for one type of chip multi-processors is also discussed. The SHCA is compared with conventional error correction approaches and its strengths and limitations are analyzed
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