Inertial and Degradation Delay Model for CMOS Logic Gates

The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the Degradation Delay Model presented in previous papers with a new algorithm to handle the inertial effect, and is able to take account of the propagation and filtering of arbitrarily narrow pulses (glitches, etc.). The model clearly overcomes the limitations of conventional approaches

CMOS array design automation techniques

A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using the standard cell approach was developed, implemented, tested and validated. Basic cell design topology and guidelines are defined based on an extensive analysis that includes circuit, layout, process, array topology and required performance considerations particularly high circuit speed

Complementary Symmetry Nanowire Logic Circuits: Experimental Demonstrations and in Silico Optimizations

Complementary symmetry (CS) Boolean logic utilizes both p- and n-type field-effect transistors (FETs) so that an input logic voltage signal will turn one or more p- or n-type FETs on, while turning an equal number of n- or p-type FETs off. The voltage powering the circuit is prevented from having a direct pathway to ground, making the circuit energy efficient. CS circuits are thus attractive for nanowire logic, although they are challenging to implement. CS logic requires a relatively large number of FETs per logic gate, the output logic levels must be fully restored to the input logic voltage level, and the logic gates must exhibit high gain and robust noise margins. We report on CS logic circuits constructed from arrays of 16 nm wide silicon nanowires. Gates up to a complexity of an XOR gate (6 p-FETs and 6 n-FETs) containing multiple nanowires per transistor exhibit signal restoration and can drive other logic gates, implying that large scale logic can be implemented using nanowires. In silico modeling of CS inverters, using experimentally derived look-up tables of individual FET properties, is utilized to provide feedback for optimizing the device fabrication process. Based upon this feedback, CS inverters with a gain approaching 50 and robust noise margins are demonstrated. Single nanowire-based logic gates are also demonstrated, but are found to exhibit significant device-to-device fluctuations

Layout level design for testability strategy applied to a CMOS cell library

The layout level design for testability (LLDFT) rules used here allow to avoid some hard to detect faults or even undetectable faults on a cell library by modifying the cell layout without changing their behavior and achieving a good level of reliability. These rules avoid some open faults or reduce their appearance probability. The main purpose has been to apply that set of LLDFT rules on the cells of the library designed at the Centre Nacional de Microelectronica (CNM) in order to obtain a highly testable cell library. The authors summarize the main results (area overhead and performance degradation) of the application of the LLDFT rules on the cell

Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification