MATIC: Learning Around Errors for Efficient Low-Voltage Neural Network Accelerators

As a result of the increasing demand for deep neural network (DNN)-based services, efforts to develop dedicated hardware accelerators for DNNs are growing rapidly. However,while accelerators with high performance and efficiency on convolutional deep neural networks (Conv-DNNs) have been developed, less progress has been made with regards to fully-connected DNNs (FC-DNNs). In this paper, we propose MATIC (Memory Adaptive Training with In-situ Canaries), a methodology that enables aggressive voltage scaling of accelerator weight memories to improve the energy-efficiency of DNN accelerators. To enable accurate operation with voltage overscaling, MATIC combines the characteristics of destructive SRAM reads with the error resilience of neural networks in a memory-adaptive training process. Furthermore, PVT-related voltage margins are eliminated using bit-cells from synaptic weights as in-situ canaries to track runtime environmental variation. Demonstrated on a low-power DNN accelerator that we fabricate in 65 nm CMOS, MATIC enables up to 60-80 mV of voltage overscaling (3.3x total energy reduction versus the nominal voltage), or 18.6x application error reduction.Comment: 6 pages, 12 figures, 3 tables. Published at Design, Automation and Test in Europe Conference and Exhibition (DATE) 201

Advanced Integrated Power and Attitude Control System (IPACS) study

Integrated Power and Attitude Control System (IPACS) studies performed over a decade ago established the feasibility of simultaneously satisfying the demands of energy storage and attitude control through the use of rotating flywheels. It was demonstrated that, for a wide spectrum of applications, such a system possessed many advantages over contemporary energy storage and attitude control approaches. More recent technology advances in composite material rotors, magnetic suspension systems, and power control electronics have triggered new optimism regarding the applicability and merits of this concept. This study is undertaken to define an advanced IPACS and to evaluate its merits for a space station application. System and component designs are developed to establish the performance of this concept and system trade studies conducted to examine the viability of this approach relative to conventional candidate systems. It is clearly demonstrated that an advanced IPACS concept is not only feasible, but also offers substantial savings in mass and life-cycle cost for the space station mission

The Design of a System Architecture for Mobile Multimedia Computers

This chapter discusses the system architecture of a portable computer, called Mobile Digital Companion, which provides support for handling multimedia applications energy efficiently. Because battery life is limited and battery weight is an important factor for the size and the weight of the Mobile Digital Companion, energy management plays a crucial role in the architecture. As the Companion must remain usable in a variety of environments, it has to be flexible and adaptable to various operating conditions. The Mobile Digital Companion has an unconventional architecture that saves energy by using system decomposition at different levels of the architecture and exploits locality of reference with dedicated, optimised modules. The approach is based on dedicated functionality and the extensive use of energy reduction techniques at all levels of system design. The system has an architecture with a general-purpose processor accompanied by a set of heterogeneous autonomous programmable modules, each providing an energy efficient implementation of dedicated tasks. A reconfigurable internal communication network switch exploits locality of reference and eliminates wasteful data copies

A battery hardware-in-the-loop setup for concurrent design and evaluation of real-time optimal HEV power management controllers

Razavian, R. S., Azad, N. L., & McPhee, J. (2013). A battery hardware-in-the-loop setup for concurrent design and evaluation of real-time optimal HEV power management controllers. International Journal of Electric and Hybrid Vehicles, 5(3), 177. Final version published by Inderscience Publishers, and available at: https://doi.org/10.1504/IJEHV.2013.057604We have developed a battery hardware-in-the-loop (HIL) setup, which can expedite the design and evaluation of power management controllers for hybrid electric vehicles (HEVs) in a novel cost- and time-effective manner. The battery dynamics have a significant effect on the HEV power management controller design; therefore, physical batteries are included in the simulation loop for greater simulation fidelity. We use Buckingham's Pi Theorem in the scaled-down battery HIL setup to reduce development and testing efforts, while maintaining the flexibility and fidelity of the control loop. In this paper, usefulness of the setup in parameter identification of a simple control-oriented battery model is shown. The model is then used in the power management controller design, and the real-time performance of the designed controller is tested with the same setup in a realistic control environment. Test results show that the designed controller can accurately capture the dynamics of the real system, from which the assumptions made in its design process can be confidently justified.Financial support for this research has been provided by the Natural Sciences and Engineering Research Council of Canada (NSERC), Toyota, and Maplesoft

Exploring performance and power properties of modern multicore chips via simple machine models

Modern multicore chips show complex behavior with respect to performance and power. Starting with the Intel Sandy Bridge processor, it has become possible to directly measure the power dissipation of a CPU chip and correlate this data with the performance properties of the running code. Going beyond a simple bottleneck analysis, we employ the recently published Execution-Cache-Memory (ECM) model to describe the single- and multi-core performance of streaming kernels. The model refines the well-known roofline model, since it can predict the scaling and the saturation behavior of bandwidth-limited loop kernels on a multicore chip. The saturation point is especially relevant for considerations of energy consumption. From power dissipation measurements of benchmark programs with vastly different requirements to the hardware, we derive a simple, phenomenological power model for the Sandy Bridge processor. Together with the ECM model, we are able to explain many peculiarities in the performance and power behavior of multicore processors, and derive guidelines for energy-efficient execution of parallel programs. Finally, we show that the ECM and power models can be successfully used to describe the scaling and power behavior of a lattice-Boltzmann flow solver code.Comment: 23 pages, 10 figures. Typos corrected, DOI adde

Chapter One – An Overview of Architecture-Level Power- and Energy-Efficient Design Techniques

Power dissipation and energy consumption became the primary design constraint for almost all computer systems in the last 15 years. Both computer architects and circuit designers intent to reduce power and energy (without a performance degradation) at all design levels, as it is currently the main obstacle to continue with further scaling according to Moore's law. The aim of this survey is to provide a comprehensive overview of power- and energy-efficient “state-of-the-art” techniques. We classify techniques by component where they apply to, which is the most natural way from a designer point of view. We further divide the techniques by the component of power/energy they optimize (static or dynamic), covering in that way complete low-power design flow at the architectural level. At the end, we conclude that only a holistic approach that assumes optimizations at all design levels can lead to significant savings.Peer ReviewedPostprint (published version