Nanowire transistor solutions for 5nm and beyond

In this paper we present a comprehensive computational study of silicon nanowire transistor (SNT) and a SNM SRAM cell based on advanced design technology co-optimization (DTCO) TCAD tools. Utilizing this methodology, we provide guidelines and solutions for 5 nm and beyond in CMOS technology. At first, drift-diffusion (DD) results are fully calibrated against a Poisson-Schrodinger (PS) solution to calibrate density-gradient quantum corrections, and ensemble Monte Carlo (EMC) simulations to calibrate transport models. The calibrated DD gives us the capability to simulate statistical variability in nanowire transistors of the 5nm node and beyond accurately and efficiently. Various SNT structures are evaluated in terms of device figures of merit, and optimization of SNTs in terms of electrostatics driven performance is carried out. A variability-aware hierarchical compact model approach for SNT is adopted and used for statistical SRAM simulation near the scaling limit. The scaling of SNTs beyond the 5 nm is also discussed. ? 2016 IEEE.EI269-2742016-Ma

Skybridge-3D-CMOS: A Fine-Grained Vertical 3D-CMOS Technology Paving New Direction for 3D IC

2D CMOS integrated circuit (IC) technology scaling faces severe challenges that result from device scaling limitations, interconnect bottleneck that dominates power and performance, etc. 3D ICs with die-die and layer-layer stacking using Through Silicon Vias (TSVs) and Monolithic Inter-layer Vias (MIVs) have been explored in recent years to generate circuits with considerable interconnect saving for continuing technology scaling. However, these 3D IC technologies still rely on conventional 2D CMOS’s device, circuit and interconnect mindset showing only incremental benefits while adding new challenges reliability issues, robustness of power delivery network design and short-channel effects as technology node scaling. Skybridge-3D-CMOS (S3DC) is a fine-grained 3D IC fabric that uses vertically-stacked gates and 3D interconnections composed on vertical nanowires to yield orders of magnitude benefits over 2D ICs. This 3D fabric fully uses the vertical dimension instead of relying on a multi-layered 2D mindset. Its core fabric aspects including device, circuit-style, interconnect and heat-extraction components are co-architected considering the major challenges in 3D IC technology. In S3DC, the 3D interconnections provide greater routing capacity in both vertical and horizontal directions compared to conventional 3D ICs, which eliminates the routability issue in conventional 3D IC technology while enabling ultra-high density design and significant benefits over 2D. Also, the improved vertical routing capacity in S3DC is beneficial for achieving robust and high-density power delivery network (PDN) design while conventional 3D IC has design issues in PDN design due to limited routing resource in vertical direction. Additionally, the 3D gate-all-around transistor incorporating with 3D interconnect in S3DC enables significant SRAM design benefits and good tolerance of process variation compared to conventional 3D IC technology as well as 2D CMOS. The transistor-level (TR-L) monolithic 3D IC (M3D) is the state-of-the-art monolithic 3D technology which shows better benefits than other M3D approaches as well as the TSV-based 3D IC approach. The S3DC is evaluated in large-scale benchmark circuits with comparison to TR-L M3D as well as 2D CMOS. Skybridge yields up to 3x lower power against 2D with no routing congestion in benchmark circuits while TR-L M3D only has up-to 22% power saving with severe routing congestions in the design. The PDN design in S3DC show

Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS

Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, scaling to sub-20nm technologies is proving to be challenging as MOSFETs are reaching their fundamental limits and interconnection bottleneck is dominating IC operational power and performance. Migrating to 3-D, as a way to advance scaling, has eluded us due to inherent customization and manufacturing requirements in CMOS that are incompatible with 3-D organization. Partial attempts with die-die and layer-layer stacking have their own limitations. We propose a 3-D IC fabric technology, Skybridge[TM], which offers paradigm shift in technology scaling as well as design. We co-architect Skybridge's core aspects, from device to circuit style, connectivity, thermal management, and manufacturing pathway in a 3-D fabric-centric manner, building on a uniform 3-D template. Our extensive bottom-up simulations, accounting for detailed material system structures, manufacturing process, device, and circuit parasitics, carried through for several designs including a designed microprocessor, reveal a 30-60x density, 3.5x performance per watt benefits, and 10X reduction in interconnect lengths vs. scaled 16-nm CMOS. Fabric-level heat extraction features are shown to successfully manage IC thermal profiles in 3-D. Skybridge can provide continuous scaling of integrated circuits beyond CMOS in the 21st century.Comment: 53 Page

Influence of surface stoichiometry and quantum confinement on the electronic structure of small diameter InxGa1-xAs nanowires

Electronic structures for InxGa1-xAs nanowires with [100], [110], and [111] orientations and critical dimensions of approximately 2 nm are treated within the framework of density functional theory. Explicit band structures are calculated and properties relevant to nanoelectronic design are extracted including band gaps, effective masses, and density of states. The properties of these III-V nanowires are compared to silicon nanowires of comparable dimensions as a reference system. In nonpolar semiconductors, quantum confinement and surface chemistry are known to play a key role in the determination of nanowire electronic structure. InxGa1-xAs nanowires have in addition effects due to alloy stoichiometry on the cation sublattice and due to the polar nature of the cleaved nanowire surfaces. The impact of these additional factors on the electronic structure for these polar semiconductor nanowires is shown to be significant and necessary for accurate treatment of electronic structure properties

Modelling and simulation study of NMOS Si nanowire transistors

Nanowire transistors (NWTs) represent a potential alternative to Silicon FinFET technology in the 5nm CMOS technology generation and beyond. Their gate length can be scaled beyond the limitations of FinFET gate length scaling to maintain superior off-state leakage current and performance thanks to better electrostatic control through the semiconductor nanowire channels by gate-all-around (GAA) architecture. Furthermore, it is possible to stack nanowires to enhance the drive current per footprint. Based on these considerations, vertically-stacked lateral NWTs have been included in the latest edition of the International Technology Roadmap for Semiconductors (ITRS) to allow for further performance enhancement and gate pitch scaling, which are key criteria of merit for the new CMOS technology generation. However, electrostatic confinement and the transport behaviour in these devices are more complex, especially in or beyond the 5nm CMOS technology generation. At the heart of this thesis is the model-based research of aggressively-scaled NWTs suitable for implementation in or beyond the 5nm CMOS technology generation, including their physical and operational limitations and intrinsic parameter fluctuations. The Ensemble Monte Carlo approach with Poisson-Schrödinger (PS) quantum corrections was adopted for the purpose of predictive performance evaluation of NWTs. The ratio of the major to the minor ellipsoidal cross-section axis (cross-sectional aspect ratio - AR) has been identified as a significant contributing factor in device performance. Until now, semiconductor industry players have carried out experimental research on NWTs with two different cross-sections: circular cylinder (or elliptical) NWTs and nanosheet (or nanoslab) NWTs. Each version has its own benefits and drawbacks; however, the key difference between these two versions is the cross-sectional AR. Several critical design questions, including the optimal NWT cross-sectional aspect ratio, remain unanswered. To answer these questions, the AR of a GAA NWT has been investigated in detail in this research maintaining the cross-sectional area constant. Signatures of isotropic charge distributions within Si NWTs were observed, exhibiting the same attributes as the golden ratio (Phi), the significance of which is well-known in the fields of art and architecture. To address the gap in the existing literature, which largely explores NWT scaling using single-channel simulation, thorough simulations of multiple channels vertically-stacked NWTs have been carried out with different cross-sectional shapes and channel lengths. Contact resistance, non-equilibrium transport and quantum confinement effects have been taken into account during the simulations in order to realistically access performance and scalability. Finally, the individual and combined effects of key statistical variability (SV) sources on threshold voltage (VT), subthreshold slope (SS), ON-current (Ion) and drain-induced barrier lowering (DIBL) have been simulated and discussed. The results indicate that the variability of NWTs is impacted by device architecture and dimensions, with a significant reduction in SV found in NWTs with optimal aspect ratios. Furthermore, a reduction in the variability of the threshold voltage has been observed in vertically-stacked NWTs due to the cancelling-out of variability in double and triple lateral channel NWTs

Strain integration and performance optimization in sub-20nm FDSOI CMOS technology

La technologie CMOS à base de Silicium complètement déserté sur isolant (FDSOI) est considérée comme une option privilégiée pour les applications à faible consommation telles que les applications mobiles ou les objets connectés. Elle doit cela à son architecture garantissant un excellent comportement électrostatique des transistors ainsi qu'à l'intégration de canaux contraints améliorant la mobilité des porteurs. Ce travail de thèse explore des solutions innovantes en FDSOI pour nœuds 20nm et en deçà, comprenant l'ingénierie de la contrainte mécanique à travers des études sur les matériaux, les dispositifs, les procédés d'intégration et les dessins des circuits. Des simulations mécaniques, caractérisations physiques (µRaman), et intégrations expérimentales de canaux contraints (sSOI, SiGe) ou de procédés générant de la contrainte (nitrure, fluage de l'oxyde enterré) nous permettent d'apporter des recommandations pour la technologie et le dessin physique des transistors en FDSOI. Dans ce travail de thèse, nous avons étudié le transport dans les dispositifs à canal court, ce qui nous a amené à proposer une méthode originale pour extraire simultanément la mobilité des porteurs et la résistance d'accès. Nous mettons ainsi en évidence la sensibilité de la résistance d'accès à la contrainte que ce soit pour des transistors FDSOI ou nanofils. Nous mettons en évidence et modélisons la relaxation de la contrainte dans le SiGe apparaissant lors de la gravure des motifs et causant des effets géométriques (LLE) dans les technologies FDSOI avancées. Nous proposons des solutions de type dessin ainsi que des solutions technologiques afin d'améliorer la performance des cellules standard digitales et de mémoire vive statique (SRAM). En particulier, nous démontrons l'efficacité d'une isolation duale pour la gestion de la contrainte et l'extension de la capacité de polarisation arrière, qui un atout majeur de la technologie FDSOI. Enfin, la technologie 3D séquentielle rend possible la polarisation arrière en régime dynamique, à travers une co-optimisation dessin/technologie (DTCO).The Ultra-Thin Body and Buried oxide Fully Depleted Silicon On Insulator (UTBB FDSOI) CMOS technology has been demonstrated to be highly efficient for low power and low leakage applications such as mobile, internet of things or wearable. This is mainly due to the excellent electrostatics in the transistor and the successful integration of strained channel as a carrier mobility booster. This work explores scaling solutions of FDSOI for sub-20nm nodes, including innovative strain engineering, relying on material, device, process integration and circuit design layout studies. Thanks to mechanical simulations, physical characterizations and experimental integration of strained channels (sSOI, SiGe) and local stressors (nitride, oxide creeping, SiGe source/drain) into FDSOI CMOS transistors, we provide guidelines for technology and physical circuit design. In this PhD, we have in-depth studied the carrier transport in short devices, leading us to propose an original method to extract simultaneously the carrier mobility and the access resistance and to clearly evidence and extract the strain sensitivity of the access resistance, not only in FDSOI but also in strained nanowire transistors. Most of all, we evidence and model the patterning-induced SiGe strain relaxation, which is responsible for electrical Local Layout Effects (LLE) in advanced FDSOI transistors. Taking into account these geometrical effects observed at the nano-scale, we propose design and technology solutions to enhance Static Random Access Memory (SRAM) and digital standard cells performance and especially an original dual active isolation integration. Such a solution is not only stress-friendly but can also extend the powerful back-bias capability, which is a key differentiating feature of FDSOI. Eventually the 3D monolithic integration can also leverage planar Fully-Depleted devices by enabling dynamic back-bias owing to a Design/Technology Co-Optimization

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Challenges and solutions for large-scale integration of emerging technologies

Title from PDF of title page viewed June 15, 2021Dissertation advisor: Mostafizur RahmanVitaIncludes bibliographical references (pages 67-88)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2021The semiconductor revolution so far has been primarily driven by the ability to shrink devices and interconnects proportionally (Moore's law) while achieving incremental benefits. In sub-10nm nodes, device scaling reaches its fundamental limits, and the interconnect bottleneck is dominating power and performance. As the traditional way of CMOS scaling comes to an end, it is essential to find an alternative to continue this progress. However, an alternative technology for general-purpose computing remains elusive; currently pursued research directions face adoption challenges in all aspects from materials, devices to architecture, thermal management, integration, and manufacturing. Crosstalk Computing, a novel emerging computing technique, addresses some of the challenges and proposes a new paradigm for circuit design, scaling, and security. However, like other emerging technologies, Crosstalk Computing also faces challenges like designing large-scale circuits using existing CAD tools, scalability, evaluation and benchmarking of large-scale designs, experimentation through commercial foundry processes to compete/co-exist with CMOS for digital logic implementations. This dissertation addresses these issues by providing a methodology for circuit synthesis customizing the existing EDA tool flow, evaluating and benchmarking against state-of-the-art CMOS for large-scale circuits designed at 7nm from MCNC benchmark suits. This research also presents a study on Crosstalk technology's scalability aspects and shows how the circuits' properties evolve from 180nm to 7nm technology nodes. Some significant results are for primitive Crosstalk gate, designed in 180nm, 65nm, 32nm, and 7nm technology nodes, the average reduction in power is 42.5%, and an average improvement in performance is 34.5% comparing to CMOS for all mentioned nodes. For benchmarking large-scale circuits designed at 7nm, there are 48%, 57%, and 10% improvements against CMOS designs in terms of density, power, and performance, respectively. An experimental demonstration of a proof-of-concept prototype chip for Crosstalk Computing at TSMC 65nm technology is also presented in this dissertation, showing the Crosstalk gates can be realized using the existing manufacturing process. Additionally, the dissertation also provides a fine-grained thermal management approach for emerging technologies like transistor-level 3-D integration (Monolithic 3-D, Skybridge, SN3D), which holds the most promise beyond 2-D CMOS technology. However, such 3-D architectures within small form factors increase hotspots and demand careful consideration of thermal management at all integration levels. This research proposes a new direction for fine-grained thermal management approach for transistor-level 3-D integrated circuits through the insertion of architected heat extraction features that can be part of circuit design, and an integrated methodology for thermal evaluation of 3-D circuits combining different simulation outcomes at advanced nodes, which can be integrated to traditional CAD flow. The results show that the proposed heat extraction features effectively reduce the temperature from a heated location. Thus, the dissertation provides a new perspective to overcome the challenges faced by emerging technologies where the device, circuit, connectivity, heat management, and manufacturing are addressed in an integrated manner.Introduction and motivation -- Cross talk computing overview -- Logic simplification approach for Crosstalk circuit design -- Crostalk computing scalability study: from 180 nm to 7 nm -- Designing large*scale circuits in Crosstalk at 7 nm -- Comparison and benchmarking -- Experimental demonstration of Crosstalk computing -- Thermal management challenges and mitigation techniques for transistor-level- 3D integratio

A Study of the Scaling and Advanced Functionality Potential of Phase Change Memory Devices

As traditional volatile and non-volatile data storage and memory technologies such as SRAM, DRAM, Flash and HDD face fundamental scaling challenges, scientists and engineers are forced to search for and develop alternative technologies for future electronic and computing systems that are relatively free from scaling issues, have lower power consumptions, higher storage densities, faster speeds, and can be easily integrated on-chip with microprocessor cores. This thesis focuses on the scaling and advanced functionality potential of one such memory technology i.e. Phase Change Memory (PCM), which is a leading contender to complement or even replace the above mentioned traditional technologies. In the first part of the thesis, a physically-realistic Multiphysics Cellular Automata PCM device modelling approach was used to study the scaling potential of conventional and commercially-viable PCM devices. It was demonstrated that mushroom-type and patterned probe PCM devices can indeed be scaled down to ultrasmall (single-nanometer) dimensions, and in doing so, ultralow programming currents (sub-20 μA) and ultrahigh storage densities (~10 Tb/in2) can be achieved via such a scaling process. Our sophisticated modelling approach also provided a detailed insight into some key PCM device characteristics, such as amorphization (Reset) and crystallization (Set) kinetics, thermal confinement, and the important resistance window i.e. difference in resistances between the Reset and Set states. In the second part of the thesis, the aforementioned modelling approach was used to assess the feasibility of some advanced functionalities of PCM devices, such as neuromorphic computing and phase change metadevices. It was demonstrated that by utilizing the accumulation mode of operation inherent to phase change materials, we can combine a physical PCM device with an external comparator-type circuit to deliver a ‘self-resetting spiking phase change neuron’, which when combined with phase change synapses can potentially open a new route for the realization of all-phase change neuromorphic computers. It was further shown that it is indeed feasible to design and ‘electrically’ switch practicable phase change metadevices (for absorber and modulator applications, and suited to operation in the technologically important near-infrared range of the spectrum). Finally, it was demonstrated that the Gillespie Cellular Automata (GCA) phase change model is capable of exhibiting ‘non-Arrhenius kinetics of crystallization’, which were found to be in good agreement with reported experimental studies

Démonstration de l'intérêt des dispositifs multi-grilles auto-alignées pour les noeuds sub-10nm.

Les nombreuses modifications de la structure du transistor bulk ont permis de poursuivre la miniaturisation jusqu'à sa limite aux nœuds 32/28nm. Les technologies actuelles répondent au besoin d'un meilleur contrôle électrostatique en s'ouvrant vers l'industrialisation de transistors complètement dépletés, avec les architectures sur film mince (FDSOI) ou non planaires (TriGate FinFET bulk). Dans ce dernier cas, le substrat bulk reste limitant pour des applications à basse consommation. La combinaison de la technologie SOI et d'une architecture non-planaire conduit aux transistors TriGate sur SOI (ou TGSOI). Nous verrons l'intérêt de ces dispositifs et démontrerons qu'ils sont compatibles avec les techniques de contrainte. On montrera en particulier les améliorations de mobilité et de courants obtenus sur ces dispositifs de largeur inférieure à 15nm. Des simulations montrent également qu'un dispositif TGSOI peut être compatible avec les techniques de modulation de VT. Enfin, nous démontrons la possibilité de fabriquer des dispositifs ultimes à nanofils empilés avec une grille enrobante par une technique innovante de lithographie tridimensionnelle. La conception, la caractérisation physique et les premiers résultats électriques obtenus seront présentés. Ces solutions peuvent répondre aux besoins des nœuds sub-10nm.Changing the bulk transistor structure was sufficient so far to fulfill the scaling needs. The current technologies answer the needs of electrostatics control with the industrialization of fully depleted transistors, with thin-film (FDSOI) or non-planar (TriGate FinFet bulk) technologies. In the latter, bulk substrate is still an issue for low power applications. Combining SOI with multiple-gate structure gives rise to TriGate on SOI (or TGSOI). We will discuss the interest of such devices and will demonstrate their compatibility with strain techniques. We will focus on the mobility and current enhancement obtained on sub-15nm width devices. Simulations also demonstrate the compatibility of TGSOI with VT modulation technique. Finally, we demonstrate the fabrication through 3D lithography of ultimate stacked nanowires with a gate-all-around. The conception, physical characterization and first electrical results are presented.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF