Downscaling and Short Channel Effects in Twin Gate Junctionless Vertical Slit FETs

we present the performance constraints in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier lowering is investigated with respect to key technological parameters, namely, the doping level in the channel, the minimum slit width, and the effective radius of the slit. This work could serve as a guideline for technology optimization, design and scaling of JL VeSFETs

Interconnect Fabric Reconfigurability for Network on Chip

Microprocessor architectures are evolving at a pace greater than ever before. To meet the industry’s stringent power, performance and cost demands there is a rising trend towards building heterogeneous processors with both CPU cores and off-chip components on the same chip. This is known as a System on Chip. These systems show promising solutions including chip interconnects consisting of Network on Chips (NoCs). These NoCs are composed of routers that control traffic, and channels used to connect different components of the chip itself together. Depending on the processor core's type, specifications, and technology used, the NoC fabrics may consume anywhere ranging from 28% to 40% of the total system power. To reduce this significant power consumption, various solutions were proposed targeting CMOS technology. In this work we focus on NoC topology improvements and reconfigurability using novel VeSFET technology. The work deploys tools used to simulate full systems, such as GPGPUSIM, to evaluate the possible performance/power gains of a hybrid CMOS-VeSFET system. This hybrid system includes CMOS core and memory layers, while the NoC layer is made up of VeSFET transistors. This allows for shorter wire lengths between routers and cores, as well as it permits for extra area to include network reconfigurability features. The necessary modifications to build this hybrid system are area changes due to VeSFET additional layer, routing length changes, pipelining changes, and VeSFET technology parameter additions. The tools modifications necessary to include this system are described in further details in this thesis. The gathered data indicates great promise for the hybrid reconfigurable CMOS-VeSFET system over the conventional non-reconfigurable CMOS system. It is demonstrated that the hybrid VeSFET system has both a power decrease of approximately 57.0% and a performance increase of approximately 50.2%

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

Structural and Optical Characterization of III-V Nanostructures Monolithically Grown on Si Substrates

Group III-V semiconductor nanostructures have emerged as an important material platform over the past decades for wide-range device implementation in the field of electronics and optoelectronics. Among them, nanowires (NWs) are particularly attractive owing to the elastic strain relaxation through their sidewall facets which allows for the combination of lattice mismatched materials. Hence, optically active III-V materials become compatible with the mature and prevalent Si platform. Moreover, NWs are ideal for hosting quantum dots (QDs) ensuring their deterministic positioning and uniformity. This configuration opens the route for sophisticated applications including single photon emission, a crucial function in quantum information processing. In addition, another type of nanostructures that has attracted attention is the two-dimensional nanosheets, whose principal benefit is the band structure tuning from bulk to 2D by modulation of their thickness. Consequently, they are established as promising blocks for various optoelectronic devices and applications. In the current thesis, we reported the growth of self-catalysed AlGaAs NWs monolithically on Si (111) substrates via solid-source molecular beam epitaxy (MBE). The self-formation of an Al-rich shell is exhibited, which is thicker at the base and thins down towards the NW tip, while it demonstrates wide alloy fluctuations. The predominantly ZB structure presents twin defects and occasional WZ insertions, further increasing the intricacy of the NWs. The optical probing via photoluminescence reveals fully tuneable emission with the Al content of the alloy. Among the morphological variations of AlGaAs NWs, the branched NWs are of unique interest. The branching events increase with Al content, while the branches are confirmed to grow on the NW trunks epitaxially. In addition, complex compositional distribution in the branches is presented, as Ga-rich stripes along the growth direction of the branches, attributed to the different nucleation energies on different faces at the liquid/solid interface of the branch, intersect with Ga-rich stripes perpendicular to them, deriving from the rotation of the sample during growth. Moreover, self-catalysed, single GaAs/AlGaAs dot-in-wire structures have been designed and grown by inserting a short GaAs segment in each AlGaAs NW. The exhaustive optical probing reveals centrally localized peaks, with a decently narrow linewidth of roughly 490 μeV. The QD emission is comprised of an exciton and a biexciton transition, while a high degree of polarization is noticed when compared to the AlGaAs NW-related emission. The above characteristics are important steps towards achieving single photon emission. Finally, we optically inspect InAs nanosheets grown via MBE via photoluminescence measurements. Pristine nanosheets exhibit surface charge via carrier trapping mechanisms at the surface states, which is suggestive of the “memory effect”. The impact of sulphur passivation and core/shell configuration on the optical response of the nanosheets is evaluated. In addition, we fabricated an optoelectronic memory unit based on pristine InAs nanosheets, adopting a field-effect transistor configuration, which demonstrates negative photoresponse with good reproducibility and ultra-low power consumption

Ordering of Epitaxial Semiconductor Nanostructures Using In Situ Pulsed Laser Interference Patterning

Low-dimensional semiconductor nanostructures have received enormous research attention by virtue of their unique electronic structure and have shown major potential for applications in nanoelectronics, nanophotonics, and optoelectronics. In particular, III-V semiconductor quantum dots (QDs), quantum dot molecules (QDMs) and quantum rings (QRs) are deemed to be promising building blocks for quantum information processing and communications. Self-assembly during epitaxial growth has enabled the production of these structures with high crystalline and optical quality. However, self-assembly also comes with stochastic nucleation and size inhomogeneity, which can limit their potential for device integration where precise positioning and nanostructures with predictable and ideally identical electronic properties are demanded. Site-controlled growth of nanostructures using ex situ lithographic techniques presents an attractive approach; nevertheless, this involves complex fabrication processes and the resulting properties of the structures have not, in general, matched those of random self-assembled nanostructures. This dissertation seeks to develop an innovative approach to laterally align high-quality epitaxial semiconductor nanostructures using an in situ patterning process based on the direct application of optical methods. In this work, an in situ technique combining nanosecond pulsed direct laser interference patterning (DLIP) with molecular beam epitaxy (MBE) growth is introduced, which offers a fast, high-efficiency route to realise the lateral ordering of semiconductor nanostructures. In the first part, the epitaxial growth and characterisation of Stranski-Krastanov (S-K) InAs QD and QDM arrays on GaAs substrates are investigated. The nanoisland arrays induced by single-pulse four-beam DLIP are observed to act as preferential nucleation sites for InAs QDs and result in a site occupancy dependent on the growth and interference parameters. The influences of both the DLIP conditions and the epitaxial growth parameters on the ordering of InAs/GaAs QDs are discussed. Precisely ordered arrays of single InAs QDs are fabricated for the first time using this in situ and non-invasive approach. The patterned QD arrays exhibit strong photoluminescence (PL) and a narrow full width at half maxima (FWHM), indicating good size uniformity and high optical quality. The second part of the dissertation explores the fabrication of ordered GaAs/AlGaAs QD and QR arrays using the droplet epitaxy (DE) approach combined with in situ DLIP. The DE approach has emerged as an attractive method to create lattice-matched self-assembled QDs with certain advantages compared to strain-driven nucleation processes. Regular arrays of Ga droplets are initially formed on nanoisland-templated AlGaAs surfaces, which are subsequently crystallised into GaAs crystals under an arsenic flux. By optimising the growth parameters, including the deposited Ga amount, the growth temperature, and the arsenic beam equivalent pressure, highly ordered arrays of single GaAs QDs and QRs can be obtained. High optical quality and excellent size homogeneity are attained according to the low-temperature PL spectra, in which a record-narrow PL emission FWHM of ~17 meV from patterned GaAs QD arrays is observed. In the final part of the dissertation, initial studies of the selective area growth (SAG) of GaAs droplets and nanocrystals on Si (100) & (111) substrates, and the growth and characterisation of type-II GaSb QDs on GaAs substrates employing in situ DLIP are demonstrated. These initial investigations show that DLIP is able to structure a silicon substrate to create Si nanoisland arrays. These islands can serve as preferential nucleation sites for Ga droplets, which can then be crystallised under arsenic exposure. Further deposition of GaAs results in the formation of periodic GaAs nanocrystals on the surface, with the size and site occupancy depending on the interference and growth parameters. The lateral ordering of S-K GaSb QDs on GaAs substrates has also been obtained, with the QD nucleation again subject to DLIP-induced nanoisland arrays. Low-temperature PL spectra of the patterned ordered arrays of GaSb QDs exhibit a comparably narrow FWHM of ~50 meV and reveal the characteristics of type-II band alignment

Design Space of Twin Gate Junctionless Vertical Slit Field Effect Transistors

In this work, we present the technological constrains and limitations in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space involving the intrinsic off-current, the sub-threshold swing, and the drain induced barrier lowering is investigated with respect to the technological parameters. This work could serve as a guideline for technology optimization and design of JL VeSFETs

Reliability Abstracts and Technical Reviews 1965

No abstract availabl